ADSP-21267SKBCZ-X AD [Analog Devices], ADSP-21267SKBCZ-X Datasheet
ADSP-21267SKBCZ-X
Related parts for ADSP-21267SKBCZ-X
ADSP-21267SKBCZ-X Summary of contents
Page 1
... On-chip memory—1M Bit of on-chip SRAM and a dedicated 3M Bits of on-chip mask-programmable ROM The ADSP-21267 is available with a 150 MHz core instruction rate. For complete ordering information, see Guide on page 43 Figure 1. FUNCTIONAL BLOCK DIAGRAM ...
Page 2
... PRELIMINARY TECHNICAL DATA ADSP-21267 KEY FEATURES At 150 MHz (6.65 ns) core instruction rate, the ADSP-21267 operates at 900 MFLOPS performance whether operating on fixed or floating point data 300 MMACS sustained performance at 150 MHz Code compatibility—At assembly level, uses the same instruction set as other SHARC DSPs Super Harvard Architecture— ...
Page 3
... The ADSP-21267 SHARC DSP is a member of the SIMD SHARC family of DSPs featuring Analog Devices' Super Har- vard Architecture. The ADSP-21267 is source code compatible with the ADSP-2136x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (Sin- gle-Instruction, Single-Data) mode. Like other SHARC DSPs, ...
Page 4
... Data Address Generators With Zero-Overhead Hardware Circular Buffer Support The ADSP-21267’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient program- ming of delay lines and other data structures required in digital Rev ...
Page 5
... I/O processor single cycle. On the ADSP-21267, the SRAM can be configured as a maxi- mum of 32K words of 32-bit data, 64K words of 16-bit data, 21K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to one megabit ...
Page 6
... Serial Peripheral (Compatible) Interface Serial Peripheral Interface (SPI industry standard syn- chronous serial link, enabling the ADSP-21267 SPI-compatible port to communicate with other SPI-compatible devices. SPI is an interface consisting of two data pins, one device select pin, and one clock pin full-duplex synchronous serial inter- face, supporting both master and slave modes ...
Page 7
... Latch Enable) pins are the control pins for the parallel port. Timers The ADSP-21267 has a total of four timers: a core timer able to generate periodic software interrupts and three general purpose timers that can that can generate periodic interrupts and be independently set to operate in one of three modes: • ...
Page 8
... Discrete 6.1, DTS Neo:6, and MPEG2 2 channel. Multiple S/PDIF and analog I/Os are provided to maximize end system flexibility. The ADSP-21267 is supported with a complete set of CROSSCORE™ software and hardware development tools, including Analog Devices emulators and VisualDSP++™ devel- opment environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21267 ...
Page 9
... Use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21267 architecture and functionality. For detailed information on the ADSP-2126x Family core architecture and instruction set, refer to the ADSP-2126x DSP Core Manual and the ADSP-21160 SHARC DSP Instruction Set Reference ...
Page 10
... P = Power Supply Synchronous, (A/D) = Active Drive, (O/D) = Open Drain, and T = Three-State. Function Parallel Port Address/Data. The ADSP-21267 parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode ...
Page 11
... MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 K internal pull-up resistor. SPI Master In Slave Out. If the ADSP-21267 is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP-21267 is configured as a slave, the MISO pin becomes a data transmit (output) pin, trans- mitting output data ...
Page 12
... Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21267. TRST has a 22.5 k internal pull-up resistor. Emulation Status. Must be connected to the ADSP-21267 Analog Devices DSP Tools product line of JTAG emulators target board connector only ...
Page 13
... For 16-bit data transfers, ALE latches address bits A15-A0 when asserted, followed by data bits D15-D0 when deasserted. Table 6. Address/ Data Mode Selection EP Data ALE Mode 8-bit Asserted 8-bit Deasserted 16-bit Asserted 16-bit Deasserted Rev. PrA | Page January 2004 ADSP-21267 AD7-0 AD15-8 Function Function A15-8 A23-16 D7-0 A7-0 A7-0 A15-8 D7-0 D15-8 ...
Page 14
... PRELIMINARY TECHNICAL DATA ADSP-21267 ADSP-21267 SPECIFICATIONS 1 Parameter V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT V High Level Input Voltage IH V Low Level Input Voltage IL T Ambient Operating Temperature AMB 1 Specifications subject to change without notice. 2 Applies to input and bidirectional pins: AD15-0, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKIN, CLKCFGx, RESET, TCK, TMS, TDI, TRST. ...
Page 15
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21267 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 16
... Timing requirements guarantee that the processor operates correctly with other devices. The ADSP-21267’s internal clock (a multiple of CLKIN) pro- vides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP’ ...
Page 17
... If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 Figure 6. Power Up Sequencing Rev. PrA | Page January 2004 ADSP-21267 Min Max Unit 0 ns -50 200 ms 0 200 ...
Page 18
... CKH Figure 7. Clock Input Clock Signals The ADSP-21267 can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-21267 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. the component connections used for a crystal operating in fun- Reset Table 10 ...
Page 19
... Table 12. Core Timer Parameter Switching Characteristic t CTIMER Pulse Width WCTIM Min CCLK t IPW Figure 10. Interrupts Min CCLK Figure 11. Core Timer Rev. PrA | Page January 2004 ADSP-21267 Max Unit ns Max Unit ns ...
Page 20
... PRELIMINARY TECHNICAL DATA ADSP-21267 Timer PWM_OUT Cycle Timing The following timing specification applies to Timer[2:0] in PWM_OUT (pulse width modulation) mode. Timer signals are routed to the DAI_P[20:1] pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins. Table 13. Timer[2:0] PWM_OUT Timing ...
Page 21
... For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 15. DAI Pin to Pin Routing Parameter Timing Requirement t Delay DAI Pin Input Valid to DAI Output Valid DPIO Min 3 DAI_Pn DAI_Pm t DPIO Figure 14. DAI Pin to PIN Direct Routing Rev. PrA | Page January 2004 ADSP-21267 Max Unit 10 ns ...
Page 22
... PRELIMINARY TECHNICAL DATA ADSP-21267 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the Precision Clock Generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s Table 16 ...
Page 23
... Timing Requirement t FLAG[3:0] IN Pulse Width FIPW Switching Characteristic t FLAG[3:0] OUT Pulse Width FOPW DAI_P[20:1] (FLG3-0 (AD[15:0]) DAI_P[20:1] (FLG3-0 (AD[15:0]) Min FIPW ) OUT t FOPW Figure 16. Flags Rev. PrA | Page January 2004 ADSP-21267 Max Unit +3 ns CCLK – CCLK ...
Page 24
... PRELIMINARY TECHNICAL DATA ADSP-21267 Memory Read–Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the ADSP-21267 is accessing external memory space. Table 18. 8-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data [7:0] Setup Before RD High DRS t Address/Data [7:0] Hold After RD High ...
Page 25
... ALE RD WR AD[15: ALEW t ALERW t ADAH t ADAS VALID ADDRESS t ALEHZ Figure 18. Read Cycle For 16-bit Memory Timing Rev. PrA | Page January 2004 ADSP-21267 Min Max 3 – 2 CCLK – 1 CCLK 2 – 2.0 CCLK 0 – 0.8 CCLK 0 – 0.8 ...
Page 26
... PRELIMINARY TECHNICAL DATA ADSP-21267 Memory Write—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the ADSP-21267 is accessing external memory space. Table 20. 8-bit Memory Write Cycle Parameter Switching Characteristics: t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ...
Page 27
... D – ALEW t ALERW t ALEHZ t t ADAS ADAH VALID ADDRESS Figure 20. Write Cycle For 16-bit Memory Timing Rev. PrA | Page January 2004 ADSP-21267 Max – 2 CCLK – 1 CCLK – 2.0 CCLK – 0.8 CCLK – 0.8 0.5t + 3.0 CCLK CCLK – 1 CCLK t ...
Page 28
... PRELIMINARY TECHNICAL DATA ADSP-21267 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 22. Serial Ports—External Clock ...
Page 29
... HDTE/I 1ST BIT t DDTLFSE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE t HFSE/I t SFSE/I t DDTE/I t DDTENFS t HDTE/I 1ST BIT t DDTLFSE 1 Figure 21. External Late Frame Sync Rev. PrA | Page January 2004 ADSP-21267 Max Unit Max Unit 2ND BIT 2ND BIT ...
Page 30
... PRELIMINARY TECHNICAL DATA ADSP-21267 DATA RECEIVE— INTERNAL CLOCK DRIVE EDGE t SCLKIW DAI_P[20:1] (SCLK) t DFSI t HOFSI DAI_P[20:1] (FS) DAI_P[20: A NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT — INTERNAL CLOCK ...
Page 31
... DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the Precision Clock Generators (PCG) or SPORTs. PCG's input can be either CLKIN or any of the DAI pins. DAI_P[20:1] (SCLK) DAI_P[20:1] (FS) DAI_P[20:1] (SDATA) Table 26. IDP Min 1 2.5 1 2.5 1 2 SAMPLE EDGE t IDPCLKW t SISFS t SISD Figure 23. IDP Master Timing Rev. PrA | Page January 2004 ADSP-21267 Max Unit SIHFS t SIHD ...
Page 32
... The timing requirements for the PDAP are provided in Table 27. PDAP is the parallel mode operation of channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2126x Hardware Reference Manual. Note Table 27. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements ...
Page 33
... MSB VALID LSB VALID Figure 25. SPI Master Timing Rev. PrA | Page January 2004 ADSP-21267 Min Max Unit CCLK – CCLK – ...
Page 34
... PRELIMINARY TECHNICAL DATA ADSP-21267 SPI Interface—Slave Table 29. SPI Interface Protocol —Slave Switching and Timing Specifications Parameter Timing Requirements t Serial Clock Cycle SPICLKS t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t SPIDS Assertion to First SPICLK Edge SDSCO CPHASE = 0 CPHASE = 1 ...
Page 35
... TDO SYSTEM INPUTS SYSTEM OUTPUTS Min TCK t t STAP HTAP t DTDO t t SSYS HSYS t DSYS Figure 27. IEEE 11499.1 JTAG Test Access Port Rev. PrA | Page January 2004 ADSP-21267 Max Unit ...
Page 36
... PRELIMINARY TECHNICAL DATA ADSP-21267 OUTPUT DRIVE CURRENTS Figure 28 shows typical I-V characteristics for the output driv- ers of the ADSP-21267. The curves represent the current drive capability of the output drivers as a function of output voltage TBD -10 -20 - TBD -40 0 0.5 1 1.5 2 SWEEP (V DDEXT ) VOLTAGE - V Figure 28 ...
Page 37
... ENVIRONMENTAL CONDITIONS The ADSP-21267 processor is rated for performance over the commercial temperature range 0°C to 70°C. AMB THERMAL CHARACTERISTICS The ADSP-21267 is offered in 144-lead LQFP and 136-ball BGA packages Table 31 and Table 32 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to- board measurement complies with JESD51-8 ...
Page 38
... PRELIMINARY TECHNICAL DATA ADSP-21267 136-BALL BGA PIN CONFIGURATIONS The following table shows the ADSP-21267’s pin names and their default function after reset (in parenthesis). Table 33. 136-ball BGA Pin Assignments Pin Name BGA Pin Name Pin# CLKCFG0 A01 CLKCFG1 XTAL A02 GND ...
Page 39
... K14 DAI_P14 (SFS23) P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 Rev. PrA | Page January 2004 ADSP-21267 BGA Pin Name BGA Pin# Pin# L01 AD0 M01 L02 WR M02 L04 GND M03 L05 GND M12 ...
Page 40
... PRELIMINARY TECHNICAL DATA ADSP-21267 Figure 34. 136-ball BGA Pin Assignments (Bottom View, Summary KEY V A GND* DDINT VDD V A I/O SIGNALS DDEXT VSS *USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. ...
Page 41
... PRELIMINARY TECHNICAL DATA 144-LEAD LQFP PIN CONFIGURATIONS The following table shows the ADSP-21267’s pin names and their default function after reset (in parenthesis). Table 34. 144-Lead LQFP Pin Assignments Pin Name LQFP Pin Name Pin # DDINT DDINT CLKCFG0 2 GND CLKCFG1 3 RD ...
Page 42
... PRELIMINARY TECHNICAL DATA ADSP-21267 PACKAGE DIMENSIONS The ADSP-21267 is available in a 136-ball BGA package and a 144-lead LQFP package. All dimensions are in millimeters (mm). 12.00 SQ BSC A1 BALL PAD CORNER Top View 1.70 MAX ALL DIMENSIONS IN MILIMETERS (MM). 1. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.150 MM OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES ...
Page 43
... Part Number Ambient Temper- ature Range ADSP-21267SKSTZ +70 C ADSP-21267SKBCZ + indicates commercial grade temperature ( +70 C indicates Ball Grid Array package. ST indicates Low Profile Quad Flat package indicates Lead Free package. For more information about lead free package offerings, please visit www.analog.com. ...
Page 44
... PRELIMINARY TECHNICAL DATA ADSP-21267 © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04623-0-1/04(PrA) a Rev. PrA | Page January 2004 www.analog.com ...