DSP56001FE33 MOTOROLA [Motorola, Inc], DSP56001FE33 Datasheet - Page 32

• Manufacturer Part Number: DSP56001FE33
• Description: 24-Bit General Purpose Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

MOTOROLA
32
Vcc = 5.0 Vdc + 10%, T
Vcc = 5.0 Vdc + 5%, T
The DSP56001 External Bus Timing Specifications are designed and tested at the maximum capacitive load of 50 pf, including
stray capacitance. Typically, the drive capability of the External Bus pins (A0-A15, D0-D23, PS, DS, RD, WR, X/Y) derates
linearly at 1 ns per 12 pf of additional capacitance from 50 pf to 250 pf of loading. Port B and C pins derate linearly at 1 ns per
5 pf of additional capacitance from 50 pf to 250 pf of loading.
Active low inputs should be “pulled up” in a manner consistent with the AC and DC specifications.
To conserve power, when an internal memory access follows an external memory access, the RD and WR strobes remain
deasserted and A0-A15 and X/Y do not change from their previous state. Both PS and DS will be deasserted (they do not
change between two external accesses to the same memory space) indicating that no external memory access is occurring.
If BR has been asserted, then the bus signals will be three-stated according to the timing information in this data sheet.
Num
115
116
117
118
119
120
121
122
123
124
125
126
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
WS = Number of Wait States, Determined by BCR Register (WS = 0 to 15)
Delay from BR Assertion to BG
Assertion
Flags Input Hold Time After RXC
Falling Edge Deassertion
BG Deassertion Duration
Delay from Address, Data, and Control
Bus High Impedance to BG Assertion
Delay from BG Deassertion to
Address, Data, and Control Bus
Enabled
Address Valid to WR Assertion WS=0
WR Assertion Width
WR Deassertion to Address Not Valid
WR Assertion to Data Out Valid WS=0
Data Out Hold Time from WR
Deassertion (The maximum specifica-
tion is periodically sampled, and not
100% tested.)
Data Out Setup Time to WR
Deassertion (see Note 6)
RD Deassertion to Address Not Valid
Capacitance Derating — External Bus Asynchronous Timing
Characteristics
J
J
= -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz, see Bus Figures 1 and 2
= -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz,
DSP56001 Electrical Characteristics
(see Note 2)
(see Note 3)
(see Note 4)
(see Note 1)
(see Note 5)
AC Electrical Characteristics —
WS=0
WS=0
WS>0
WS>0
WS>0
WS>0
2
2*cyc-10
WS*cyc
WS*cyc
cyc+tch
cyc+tch
*
Infinity
tch-12
cyc+tch
tch+4
2*cyc
+tcl-9
+tcl-5
cyc-9
cyc-9
tch-9
tch-9
tch-9
Min
tcl-9
tcl-5
—
0
0
20.5 MHz
cyc*WS+20
2*cyc*WS+
cyc+tch+30
4*cyc+tch+
4*cyc+tch+
6*cyc+tch+
4*cyc+20
tch+10
tch-10
cyc+5
tch+7
Max
tcl+5
20
20
10
—
—
—
—
—
—
—
—
—
2
WS*cyc
WS*cyc
cyc+tch
cyc+tch
2*cyc-8
*
Infinity
cyc+tch
tch+3
+tcl-7
+tcl-5
2*cyc
cyc-7
cyc-7
tch-9
tch-7
tch-7
tch-7
Min
tcl-7
tcl-5
—
0
0
27 MHz
cyc*WS+15
2*cyc*WS+
cyc+tch+23
4*cyc+tch+
4*cyc+tch+
6*cyc+tch+
4*cyc+15
cyc+5
tch+8
tch+6
Max
tch-8
tcl+5
15
15
—
—
—
—
—
—
—
—
—
8
2
cyc+tch
cyc+tch
WS*cyc
WS*cyc
*
2*cyc-6
cyc-5.5
cyc-5.0
+tcl-5.0
tch-7.5
tch-5.5
tch-5.5
tch-5.5
Infinity
tcl-5.5
cyc+tch
tch+3
2*cyc
+tcl-5
Min
tcl-5
—
0
0
33 MHz
cyc*WS+13
cyc+tch+19
4*cyc+tch+
4*cyc+tch+
6*cyc+tch+
2*cyc*WS+
4*cyc+13
tch+6.5
tch+4.5
cyc+5
Max
tch-6
tcl+5
6.5
13
13
—
—
—
—
—
—
—
—
—
DSP56001
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns