DSP56001FE33 MOTOROLA [Motorola, Inc], DSP56001FE33 Datasheet - Page 12

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DSP56001FE33

Manufacturer Part Number
DSP56001FE33
Description
24-Bit General Purpose Digital Signal Processor
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSP56001FE33
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
MOTOROLA
12
Num
17
18
19
20
21
22
AC Electrical Characteristics - Reset, Stop, Mode Select, and Interrupt Timing
Delay from IRQA, IRQB Assertion to
External Memory Access Address Out
Valid Caused by First Interrupt
Delay from IRQA, IRQB Assertion to
General Purpose Transfer Output Valid
Caused by First Interrupt Instruction
Execution
Delay from Address Output Valid
Caused by First Interrupt Instruction
Execution to Interrupt Request
Deassertion for Level Sensitive Fast
Interrupts
Delay from RD Assertion to Interrupt
Request Deassertion for Level
Sensitive Fast Interrupts
Delay from WR Assertion to WS=0
WS>0 Level Sensitive Fast Interrupts
Delay from General-Purpose Output
Valid to Interrupt Request Deassertion
for Level Sensitive Fast Interrupts
Interrupt Request Deassertion for
- If Second Interrupt Instruction is:
When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19 through 22 apply
to prevent multiple interrupt service. To avoid these timing restrictions, the negative edge-triggered mode is rec-
ommended when using fast interrupt. Long interrupts are recommended when using level-sensitive mode.
Characteristics
Instruction Execution
Instruction Fetch
DSP56001 Electrical Characteristics
Single Cycle
Two Cycle
5
9
*
*
11+cyc
cyc+tch
cyc+tch
Min
+tch
20.5 MHz
(Continued)
(2
NOTE
2
(cyc
(cyc
(cyc
cyc+tcl+
2
*
2
*
cyc+tcl+
*
tcl-60
Max
cyc)+tcl
*
cyc-40
-44
-40
-40
-60
cyc+
*
*
*
WS)
WS)
WS)
5
9
*
*
11
cyc+tch
cyc+tch
Min
+tch
*
cyc
27 MHz
2
(2
(cyc
(cyc
(cyc
2
cyc+tcl+
*
2
*
*
cyc+tcl+
tcl-46
Max
cyc)+tcl
cyc-31
*
-34
-31
-31
-46
cyc+
*
*
*
WS)
WS)
WS)
5
9
*
*
11
cyc+tch
cyc+tch
Min
+tch
*
cyc
33 MHz
2
(2
(cyc
(cyc
(cyc
2
cyc+tcl+
*
2
*
*
cyc+tcl+
tcl-37
Max
cyc)+tcl
*
cyc-25
-27
-25
-25
-37
cyc+
*
*
*
WS)
WS)
WS)
DSP56001
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

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