DSP56001FE33 MOTOROLA [Motorola, Inc], DSP56001FE33 Datasheet - Page 11

• Manufacturer Part Number: DSP56001FE33
• Description: 24-Bit General Purpose Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

DSP56001
AC Electrical Characteristics - Reset, Stop, Mode Select and Interrupt Timing
Num
16a
10
11
12
13
14
15
16
9
Delay from RESET Assertion to
Address High Impedance (periodically
sampled and not 100% tested)
Minimum Stabilization Duration
Delay from Asynchronous RESET
Deassertion to First External Address
Output (Internal Reset Negation)
Synchronous Reset Setup Time from
RESET Deassertion to Falling Edge of
External Clock
Synchronous Reset Delay Time from
the Synchronous Falling Edge of Exter-
nal Clock to the First External Address
Output
Mode Select Setup Time
Mode Select Hold Time
Edge-Triggered Interrupt Request
(Vcc = 5.0 Vdc +10%, T
(Vcc = 5.0 Vdc + 5%, T
(See Control Figure 1 through 8)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
WS = Number of wait states (1 WS = 1 cyc = 2T) programmed into external bus access
tch = Clock high period
tcl = Clock low period
RESET
A0-A15
Characteristics
using BCR (WS = 0 - 15)
External Clock (see Note 2)
Internal Osc. (see Note 1)
DSP56001 Electrical Characteristics
deassertion
J
J
assertion
9
= -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz)
= -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz)
Control Figure 1. Reset Timing
75000
8
25
*
8
Min
cyc+5
100
*
20
25
15
—
*
cyc
0
20.5 MHz
cyc
*
cyc
9
8
*
cyc-10
*
cyc+40
cyc+30
Max
50
—
—
—
—
—
—
10
75000*cyc
8*cyc+5
25
8*cyc
Min
—
15
77
17
10
*
0
cyc
27 MHz
9*cyc+31
8*cyc+23
cyc-8
Max
38
—
—
—
—
—
11
75000*cyc
8*cyc+5
25
8*cyc
Min
13
62
16
10
—
0
*
cyc
33 MHz
First Fetch
9*cyc+25
8*cyc+19
V
cyc-7
Max
MOTOROLA
IHR
31
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11