DAC1208D650HN NXP [NXP Semiconductors], DAC1208D650HN Datasheet - Page 19

• Manufacturer Part Number: DAC1208D650HN
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1208D650
Product data sheet
The worst case clock skew is given by δt
The minimum allowable trace delay for the MDS signal is given by Δt = δt
In real applications, the master DAC can be anywhere and both conditions must be
satisfied: δt
Example:
⇒ 200 ps + 80 ps < Δt
⇒ 280 ps < Δt
⇒ 4.2 cm < L
Fig 10. Clock skew case 2: Master is closest
•
•
•
•
clock generator skew = ± 80 ps
FR4 substrate ⇒ 15 cm/ns delay
clock trace length difference = 3 cm and 4 cm
Output sampling rate = 650 Msps
2
< Δt
mds
slave 1 clock
slave 2 clock
master clock
mds
All information provided in this document is subject to legal disclaimers.
mds
ref clock
< 17.8 cm
< 1192 ps
< TDAC − δt
Rev. 2 — 14 December 2010
mds
< 1538 ps − (266 ps + 80 ps)
2×, 4× or 8× interpolating DAC with JESD204A interface
1
.
PH01
PH02
PH03
2
= PH03 − PH01.
TDAC
DAC1208D650
001aal071
© NXP B.V. 2010. All rights reserved.
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