AD7277BRM AD [Analog Devices], AD7277BRM Datasheet - Page 5

• Manufacturer Part Number: AD7277BRM
• Description: 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
• Manufacturer: AD [Analog Devices]

N O T E S
1
2
3
4
5
6
Specifications subject to change without notice.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
REV. PrF
TIMING SPECIFICATIONS
Preliminary Technical Data
Guaranteed by Characterization. All input signals are specified with tr=tf=5ns (10% to 90% of V
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Minimum
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the Vih or Vil voltage.
t
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
timing characteristics is the true bus relinquish time of
See Power-up Time section.
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
power-up
8
SDATA
4
4
4
5
SCLK
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
OUTPUT
2
6
PIN
Figure 2. Access time after SCLK falling edge
TO
f
Figure 1. Load Circuit for Digital Output
sclk
C L
25pF
at which specifications are guaranteed.
AD7276/AD7277/AD7278
20
52
14 x t
12 x t
10 x t
T B D
10
T B D
T B D
T B D
0.4t
0.4t
T B D
T B D
T B D
T B D
Limit at T
200µA
200µA
SCLK
SCLK
Timing Specifications
t 4
SCLK
SCLK
SCLK
I OL
I OH
MIN
PRELIMINARY TECHNICAL DATA
, T
MAX
1
+1.6V
(V
DD
= +2.35 V to +3.6 V; T
KHz min
MHz max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
the part and is independent of the bus loading.
s max
V
V
Units
I H
IL
3
–5–
A
= T
AD7276
AD7277
AD7278
Minimum Quiet Time required between Bus Relinquish
and start of Next Conversion
Minimum CS Pulse Width
CS to SCLK Setup Time
Delay from CS Until SDATA Three-State Disabled
Data Access Time After SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA Three-State
SCLK Falling Edge to SDATA Three-State
Power Up Time from Full Power-down
SDATA
Description
SDATA
SCLK
SCLK
MIN
Figure 4. SCLK falling edge to SDATA Three-State
DD
to T
) and timed from a voltage level of 1.6 Volts.
Figure 3. Hold time after SCLK falling edge
V
V
IH
IL
MAX
, unless otherwise noted.)
AD7276/AD7277/AD7278
t 8
t 7
8
, quoted in the
1.4 V