AD7277BRM AD [Analog Devices], AD7277BRM Datasheet - Page 17

• Manufacturer Part Number: AD7277BRM
• Description: 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
• Manufacturer: AD [Analog Devices]

Power-up Time
The power-up time of the AD7276/AD7277/AD7278 is
TBD ns, which means that with any frequency of SCLK
up to 52 MHz, one dummy cycle will always be sufficient
to allow the device to power up. Once the dummy cycle is
complete, the ADC will be fully powered up and the input
signal will be acquired properly. The quite time t
must still be allowed from the point where the bus goes
back into three-state after the dummy conversion, to the
next falling edge of CS. When running at 3 MSPS
throughput rate, the AD7276/AD7277/AD7278 will power
up and acquire a signal within ±0.5LSB in one dummy
cycle, i.e. TBD ns.
When powering up from the Power-Down mode with a
dummy cycle, as in Figure 14, the track and hold which
was in hold mode while the part was powered down,
returns to track mode after the first SCLK edge the part
receives after the falling edge of CS. This is shown as
point A in Figure 14. Although at any SCLK frequency
one dummy cycle is sufficient to power the device up and
acquire V
dummy cycle of 16 SCLKs must always elapse to power
up the device and acquire V
cient to power the device up and acquire the input signal.
If, for example, a 25 MHz SCLK frequency was applied
to the ADC, the cycle time would be 640 ns. In one
dummy cycle, 640 ns, the part would be powered up and
V
SCLK only TBD SCLK cycles would have elapsed. At
this stage, the ADC would be fully powered up and the
signal acquired. So, in this case the CS can be brought
high after the 10th SCLK falling edge and brought low
again after a time t
When power supplies are first applied to the AD7276/
AD7277/AD7278, the ADC may either power up in the
Power-Down mode or in Normal mode. Because of this,
it is best to allow a dummy cycle to elapse to ensure the
part is fully powered up before attempting a valid
conversion. Likewise, if it is intended to keep the part in
the Power-Down mode while not in use and the user
wishes the part to power up in Power-Down mode, then
the dummy cycle may be used to ensure the device is in
Power-Down by executing a cycle such as that shown in
Figure 13. Once supplies are applied to the AD7276/
AD7277/AD7278, the power up time is the same as that
when powering up from the Power-Down mode. It takes
approximately TBD ns to power up fully if the part
powers up in Normal mode. It is not necessary to wait
TBD ns before executing a dummy cycle to ensure the
desired mode of operation. Instead, the dummy cycle can
occur directly after power is supplied to the ADC. If the
first valid conversion is then performed directly after the
dummy conversion, care must be taken to ensure that
adequate acquisition time has been allowed. As mentioned
earlier, when powering up from the Power-Down mode,
the part will return to track upon the first SCLK edge
applied after the falling edge of CS. However, when the
ADC powers up initially after supplies are applied, the
track and hold will already be in track. This means,
assuming one has the facility to monitor the ADC supply
REV. PrF
Preliminary Technical Data
IN
acquired fully. However after TBD ns with a 25 MHz
IN
, it does not necessarily mean that a full
QUIET
to initiate the conversion.
IN
fully; TBD ns will be suffi-
PRELIMINARY TECHNICAL DATA
QUIET
–17–
POWER VERSUS THROUGHPUT RATE
By using the Power-Down mode on the AD7276/AD7277/
AD7278 when not converting, the average power con-
sumption of the ADC decreases at lower throughput rates.
Figure 15 shows how as the throughput rate is reduced,
the device remains in its Power-Down state longer and the
average power consumption over time drops accordingly.
For example, if the AD7276/AD7277/AD7278 is operated
in a continuous sampling mode with a throughput rate of
500KSPS and a SCLK of 52MHz (V
device is placed in the Power-Down mode between
conversions, then the power consumption is calculated as
follows. The power dissipation during normal operation is
13.5 mW (V
cycle, i.e. 333ns, and the remaining conversion time is
another cycle, i.e. 333ns, then the AD7276/AD7277/
AD7278 can be said to dissipate 13.5mW for 666ns during
each conversion cycle.If the throughput rate is 500KSPS,
the cycle time is 2 s and the average power dissipated
during each cycle is (666/2000) x (13.5 mW)= 4.5mW.
Figure 15 shows the Power vs. Throughput Rate when
using the Power-Down mode between conversions at 3V.
The Power-Down mode is intended for use with
throughput rates of approximately TBD MSPS and under
as at higher sampling rates there is no power saving made
by using the Power-Down mode.
current, if the ADC powers up in the desired mode of
operation and thus a dummy cycle is not required to
change mode, then neither is a dummy cycle required to
place the track and hold into track.
0
0
DD
Figure 15. Power vs Throughput
= 3V). If the power up time is one dummy
AD7276/AD7277/AD7278
TBD
TITLE
DD
= 3V), and the