ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 43

• Manufacturer Part Number: ADC1443D125HD
• Description: Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
Table 43.
Default settings are shown highlighted.
Table 44.
Default settings are shown highlighted.
Table 45.
Default settings are shown highlighted.
[1]
Table 46.
Default settings are shown highlighted.
Table 47.
Default settings are shown highlighted.
Table 48.
Default settings are shown highlighted.
ADC1443D_SER
Objective data sheet
Bit
7 to 0
Bit
7 to 0
Bit
7
6
5
4
3 to 0
Bit
7
Bit
7
6 to 1
0
Bit
7 to 3
2 to 0
ILA = Initial Lane Alignment Sequence (see JESD204 JEDEC standard).
Symbol
PATTERN_IN[15:8]
Symbol
PATTERN_IN[7:0]
Symbol
RESERVED
LOOP_ALIGN
DIS_REPL_CHAR
BYP_ALIGN
RESERVED
Symbol
KEY[7:0]
Symbol
SCR[0]
RESERVED
L[0]
Symbol
RESERVED[4:0]
SWING[2:0]
CFG_3_SCR_L register (address 0822h) bit description
IP_DEBUG_IN1 register (address 0818h) bit description
IP_DEBUG_IN2 register (address 0819h) bit description
IP_TESTMODE register (address 081Bh) bit description
IP_EXPERT_DOOR register (address 081Ch) bit description
IP_OUTBUF00_SWING register (address 086Bh) bit description
Access
R/W
Access
R/W
Access
R/W
R/W
R/W
R/W
R/W
Access
R/W
Access
R/W
R/W
R/W
Access
R/W
R/W
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Rev. 03 — 19 July 2012
Value
1010 1010
Value
0000 0010
Value
0
0
0000
Value
0000 0000
Value
0
000000
0
Value
00000
000
001
010
*
0
[1]
Description
8 most significant bits of input stage debug word
(inserted in place of ADC data)
Description
8 least significant bits of input stage debug word
(inserted in place of ADC data)
Description
reserved
ILA sequence is repeated infinitely
no replacement character is placed in the data flow
ILA is bypassed
reserved
Description
8-bit key to enable Write access for JESD204 control
register
Description
scrambling enabler
reserved
lanes number minus 1 (
L = 1)
0x4A must be written in the IP_EXPERT_DOOR
registers to obtain write access to this register
Description
reserved
Configurable lane 0 output current
12 mA; 300 mV (p-p)
14 mA; 350 mV (p-p)
16 mA; 400 mV (p-p)
ADC1443D series
for example,
© IDT 2012. All rights reserved.
for two lanes
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