ADC1443D125HD IDT [Integrated Device Technology], ADC1443D125HD Datasheet - Page 33

• Manufacturer Part Number: ADC1443D125HD
• Description: Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs
• Manufacturer: IDT [Integrated Device Technology]

Table 19.
Addr.
(hex)
ADC control registers
0000h CHIP_RST
0001h CHIP_ID
0005h CHIP_RST
0006h
[2]
0007h CLK_CFG
0008h INTERNAL_
0009h CHANNEL_
0011h
0013h DIG_OFFSET
0014h TEST_CFG_1 R/W
0015h TEST_CFG_2 R/W
0016h TEST_CFG_3 R/W
0017h OTR_CFG
00FFh TRANS_CFG
JESD204A/JESD204B control
0801h IP_STATUS
0802h IP_RST
0803h IP_CFG_
0805h IP_CTRL1
Register
name
OP_MODE
REF
SEL
OUTPUT_
CFG
SETUP
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Register allocation map
11.5.2 Register allocation map
Table 19 shows an overview of all registers.
R/W
RW
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
RESERVED
RXSYNC_
ERR_FLG
SW_RST
TRANS_
Bit 7
SW_
RST
DIS
-
-
-
-
-
-
-
-
TRANSFER
TRISTATE_
CFG_PAD
Bit 6
-
-
-
-
-
-
-
-
-
-
TEST_PAT_USER[5:0]
SYNC_
Bit 5
POL
DIG_OFFSET[5:0]
-
-
-
-
-
-
-
-
-
-
-
RESERVED
SYNC_SE
TEST_PAT_USER[13:6]
SE_SEL
Bit 4
-
-
-
-
-
-
-
RESERVED[5:0]
-
-
CHIP_ID[7:0]
SW_RST[7:0]
Bit definition
RXSYNC_ERR
ASSEMBLER_
SW_RST
DIFF_SE
FAST_
[1]
Bit 3
OTR
EN_
-
-
-
-
-
-
-
DATA_
SWAP
Bit 2
CFG_STP[3:0]
-
-
-
-
-
FAST_OTR_DET[2:0]
TEST_PAT_SEL[2:0]
RESERVED[2:0]
CLK_DIV[2:0]
INTREF[2:0]
ADC_B
DATA_FORMAT[1:0]
Bit 1
OP_MODE[1:0]
-
-
-
-
-
PLL_LOCK 0000 0000
ADC_A
Bit 0
-
[3]
-
-
-
-
Default
0000 0000
0100 0011
0000 0000
0000 0000
0000 0000
0000 0000
0000 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0001 0100
0000 0000
0000 0000
0000 ****
0000 0000