AD9253-125EBZ AD [Analog Devices], AD9253-125EBZ Datasheet - Page 6

• Manufacturer Part Number: AD9253-125EBZ
• Description: Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS
• Manufacturer: AD [Analog Devices]

SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter
CLOCK
OUTPUT PARAMETERS
APERTURE
1
2
3
4
5
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
AD9253
See the
Measured on standard FR-4 material.
Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.
t
Wake-up time is defined as the time required to return to normal operation from power-down mode.
SAMPLE
Input Clock Rate
Conversion Rate
Clock Pulse Width High (t
Clock Pulse Width Low (t
Propagation Delay (t
Rise Time (t
Fall Time (t
FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DCO to FCO Delay (t
Lane Delay (t
Data to Data Skew (t
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Out-of-Range Recovery Time
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
/16 is based on the number of bits in two LVDS data lanes. t
3
AN-835 Application
1
, 2
F
R
) (20% to 80%)
) (20% to 80%)
LD
)
A
)
PD
DATA
3
FRAME
DATA-MAX
)
Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
)
EL
4
EH
)
)
4
FCO
)
CPD
− t
J
)
)
)
4
5
DATA-MIN
Description
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
See Figure 74
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to the
SCLK falling edge (not shown in Figure 74)
Time required for the SDIO pin to switch from an output to an input relative to the
SCLK rising edge (not shown in Figure 74)
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
25°C
25°C
SAMPLE
= 1/f
Min
10
10
1.5
(t
(t
Rev. 0 | Page 6 of 40
SAMPLE
SAMPLE
S
.
/16) − 300
/16) − 300
Typ
6.25/4.76/4.00
6.25/4.76/4.00
2.3
2.3
t
(t
(t
90
250
375
1
135
1
300
300
±50
16
FCO
SAMPLE
SAMPLE
+ (t
/16)
/16)
SAMPLE
/16)
Max
1000
80/105/125
3.1
(t
(t
±200
SAMPLE
SAMPLE
/16) + 300
/16) + 300
Data Sheet
Limit
0.24
0.40
2
2
40
2
2
10
10
10
10
Unit
MHz
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
ps
ns
μs
Clock cycles
ns
fs rms
Clock cycles
Unit
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns min
ns min
ns min
ns min