AD9253-125EBZ AD [Analog Devices], AD9253-125EBZ Datasheet - Page 12

• Manufacturer Part Number: AD9253-125EBZ
• Description: Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS
• Manufacturer: AD [Analog Devices]

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
0
1
2
3, 4, 7, 34, 39, 45, 46
5, 6
8, 29
9, 10
11, 12
13, 14
15, 16
17, 18
19, 20
21, 22
23, 24
25, 26
27, 28
30
31
32
33
35
36
37
38
40
41
42
43
AD9253
Mnemonic
AGND,
Exposed Pad
VIN+D
VIN−D
AVDD
CLK−, CLK+
DRVDD
D1−D, D1+D
D0−D, D0+D
D1−C, D1+C
D0−C, D0+C
DCO−, DCO+
FCO−, FCO+
D1−B, D1+B
D0−B, D0+B
D1−A, D1+A
D0−A, D0+A
SCLK/DTP
SDIO/OLM
CSB
PDWN
VIN−A
VIN+A
VIN+B
VIN−B
RBIAS
SENSE
VREF
VCM
Description
Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the
analog ground for the part. This exposed pad must be connected to ground for proper operation.
ADC D Analog Input True.
ADC D Analog Input Complement.
1.8 V Analog Supply Pins.
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
Digital Output Driver Supply.
Channel D Digital Outputs.
Channel D Digital Outputs.
Channel C Digital Outputs.
Channel C Digital Outputs.
Data Clock Outputs.
Frame Clock Outputs.
Channel B Digital Outputs.
Channel B Digital Outputs.
Channel A Digital Outputs.
Channel A Digital Outputs.
SPI Clock Input/Digital Test Pattern.
SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode.
SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up.
Digital Input, 30 kΩ Internal Pull-Down.
PDWN high = power-down device.
PDWN low = run device, normal operation.
ADC A Analog Input Complement.
ADC A Analog Input True.
ADC B Analog Input True.
ADC B Analog Input Complement.
Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
Reference Mode Selection.
Voltage Reference Input and Output.
Analog Input Common-Mode Voltage.
DRVDD
NOTES
1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE
VIN+D
VIN–D
AVDD
AVDD
AVDD
CLK+
CLK–
D1–D
D1+D
D0–D
D0+D
PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART.
THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR
PROPER OPERATION.
Figure 9. 48-Lead LFCSP Pin Configuration, Top View
10
12
11
1
2
3
4
5
6
7
8
9
(Not to Scale)
Rev. 0 | Page 12 of 40
AD9253
TOP VIEW
36
35
34
33
32
31
30
29
28
27
26
25
VIN+A
VIN–A
AVDD
PDWN
CSB
SDIO/OLM
SCLK/DTP
DRVDD
D0+A
D0–A
D1+A
D1–A
Data Sheet