AD9253-125EBZ AD [Analog Devices], AD9253-125EBZ Datasheet - Page 27

• Manufacturer Part Number: AD9253-125EBZ
• Description: Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS
• Manufacturer: AD [Analog Devices]

Data Sheet
DIGITAL OUTPUTS AND TIMING
The
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SPI. The LVDS driver current is derived on chip and sets the
output current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing (or 700 mV p-p
differential) at the receiver.
When operating in reduced range mode, the output current is
reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p
differential) across a 100 Ω termination at the receiver.
The
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is
recommended that the trace length be less than 24 inches and
that the differential output traces be close together and at equal
lengths. An example of the FCO and data stream with proper
trace length and position is shown in Figure 70. Figure 71 shows
the LVDS output timing example in reduced range mode.
Figure 70. AD9253-125, LVDS Output Timing Example in ANSI-644 Mode (Default)
AD9253
AD9253
D0 500mV/DIV
D1 500mV/DIV
DCO 500mV/DIV
FCO 500mV/DIV
differential outputs conform to the ANSI-644 LVDS
LVDS outputs facilitate interfacing with LVDS
4ns/DIV
Rev. 0 | Page 27 of 40
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histo-
gram with trace lengths less than 24 inches on standard FR-4
material is shown in Figure 72.
Figure 72. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Figure 71. AD9253-125, LVDS Output Timing Example in Reduced Range Mode
Less than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End
–100
–200
–300
–400
–500
500
400
300
200
100
7k
6k
5k
4k
3k
2k
1k
200ps
0
0
–0.8ns
D0 400mV/DIV
D1 400mV/DIV
DCO 400mV/DIV
FCO 400mV/DIV
EYE: ALL BITS
250ps
–0.4ns
300ps
Termination Only
350ps
0ns
400ps
0.4ns
ULS: 7000/400354
450ps
4ns/DIV
0.8ns
AD9253
500ps