AD9253-125EBZ AD [Analog Devices], AD9253-125EBZ Datasheet - Page 24

• Manufacturer Part Number: AD9253-125EBZ
• Description: Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS
• Manufacturer: AD [Analog Devices]

If the internal reference of the
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 60 shows
how the internal reference voltage is affected by loading.
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 61 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 54). The internal buffer generates the
positive and negative full-scale references for the ADC core. There-
fore, the external reference must be limited to a maximum of 1.0 V.
It is not recommended to leave the SENSE pin floating.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the
inputs, CLK+ and CLK−, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally
(see Figure 48) and require no external bias.
AD9253
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–2
–4
–6
–8
0
4
2
0
–40
0
0.5
Figure 60. V
–15
Figure 61. Typical V
1.0
LOAD CURRENT (mA)
TEMPERATURE (°C)
REF
10
Error vs. Load Current
AD9253
1.5
REF
INTERNAL V
AD9253
35
is used to drive multiple
Drift
2.0
sample clock
REF
60
2.5
= 1V
3.0
85
Rev. 0 | Page 24 of 40
Clock Input Options
The
can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern, as described in the Jitter Considerations
section.
Figure 62 and Figure 63 show two preferred methods for clock-
ing the AD9253 (at clock rates up to 1 GHz prior to internal CLK
divider). A low jitter clock source is converted from a single-
ended signal to a differential signal using either an RF transformer
or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 1 GHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary winding limit clock excursions into the
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the
preserving the fast rise and fall times of the signal that are critical
to achieving low jitter performance. However, the diode
capacitance comes into play at frequencies above 500 MHz. Care
must be taken in choosing the appropriate signal limiting diode.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 65. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517
excellent jitter performance.
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 66. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
CLOCK
INPUT
CLOCK
INPUT
AD9253
Figure 62. Transformer-Coupled Differential Clock (Up to 200 MHz)
Figure 63. Balun-Coupled Differential Clock (Up to 1 GHz)
50Ω
0.1µF
50Ω
has a flexible clock input structure. The clock input
0.1µF
0.1µF
100Ω
ADT1-1WT, 1:1 Z
Mini-Circuits
XFMR
0.1µF
®
0.1µF
0.1µF
0.1µF
0.1µF
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
AD9253
clock drivers offer
Data Sheet
CLK+
CLK–
CLK+
CLK–
AD9253
ADC
while
ADC
to