PCF8811U/2DA/1 NXP [NXP Semiconductors], PCF8811U/2DA/1 Datasheet - Page 29

• Manufacturer Part Number: PCF8811U/2DA/1
• Description: 80 x 128 pixels matrix LCD driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8811_4
Product data sheet
Fig 21. Write mode: a control bit followed by a transmission byte
SDATA
SCLK
SCE
Any instruction can be sent in any order to the PCF8811; the MSB is transmitted first. The
serial interface is initialized when SCE is HIGH. In this state, SCLK clock pulses have no
effect and no power is consumed by the serial interface. A falling edge on SCE enables
the serial interface and indicates the start of data transmission.
Figure
Fig 20. Serial data stream; write mode
•
•
•
•
•
•
Transmission Byte (TB) (command byte or data byte)
D/C DB7 DB6 DB5 DB4 DB3
D/C
when SCE is HIGH, SCLK clocks are ignored; during the HIGH time of SCE the serial
interface is initialized
SCLK must be LOW on the falling SCE edge; see
SDATA is sampled on the rising edge of SCLK
D/C indicates, whether the byte is a command (D/C = 0) or RAM data (D/C = 1); it is
sampled on the first rising SCLK edge
If SCE stays LOW after the last bit of a data/command byte, the serial interface
receives the D/C bit of the next byte on the next rising edge of SCLK; see
A reset pulse RES interrupts the transmission. The data being written into the RAM
may be corrupted. The registers are cleared. If SCE is LOW after the rising edge of
RES, the serial interface is ready to receive the D/C bit of a data/command byte;
see
MSB
21,
Figure
D / C
Figure 22
TB
DB7
23.
and
DB6
Rev. 04 — 27 June 2008
Figure 23
DB2 DB1 DB0
DB5
D/C
LSB
DB4
show the protocol of the write mode:
TB
DB3
DB2
80 x 128 pixels matrix LCD driver
Figure 41
DB1
D/C
DB0
TB
PCF8811
© NXP B.V. 2008. All rights reserved.
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Figure 22
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