CY7C68310 CYPRESS [Cypress Semiconductor], CY7C68310 Datasheet - Page 27

• Manufacturer Part Number: CY7C68310
• Manufacturer: CYPRESS [Cypress Semiconductor]

7.0
7.1
7.2
The CY7C68310 transceiver complies to the timing character-
istics as stated in the USB Specification version 2.0. The
CY7C68310 can operate at either the high-speed or full-speed
signalling rate.
7.3
The ATA interface supports ATA PIO modes 0 to 4, and Ultra
DMA modes 0 to 4, per the ATA Attachment – 6 with Packet
Interface revision 3b. All input signals on the ATA/ATAPI port
are considered asynchronous and are synchronized to the
chip's internal system clock. All output signals are clocked
using the chip’s internal system clock, for which there is no
external reference. Thus, the output signals should also be
considered asynchronous. The PIO mode used for data
register accesses is retrieved from the device or specified in
the CY7C68310 configuration bytes.
7.4
The CY7C68310 derives its internal system clock from an
external clock source. The external clock input signal
Document 38-08030 Rev. *H
Clock high time
Clock low time
Start condition hold time
Start condition set-up time
Data output hold time
Data output set-up time
Stop condition set-up time
Required data valid before clock
Min time bus must be free before next transmission
SDA OUT
SDA IN
SCL
I
USB Interface Timing
ATA/ATAPI Interface Timing
External Clock Source Timing
2
Timing Characteristics
C-compatible Memory Device Interface Timing
I
2
C-compatible Device Parameter
T
HD:STA
T
SU:STA
T
DSU
T
low
Figure 7-1. I
T
high
T
HD:DAT
2
C Interface Timing
frequency is measured at one half of the 2.5V power source
(VDD25). The CY7C68310 internal PLL can be clocked using
either a 30-MHz (±0.005%) fundamental-mode crystal or a
2.5V, 50% duty-cycle square wave. The recommended
external clock source for the CY7C68310 is the PRE
XH30PRF10BL crystal (10-pF load capacitance).
7.5
The CY7C68310 requires an off-chip power-on reset circuit.
nRESET must be held asserted for a minimum of 1 ms after
power is stable to cause a chip reset.
8.0
Certain external components are required for proper
CY7C68310 operation. The following figure details the
minimum required circuitry for normal operation. Additional
components may be required to support configurable
CY7C68310 features, if utilized.
Reset Timing
External Circuitry Requirements
T
SU:DAT
Symbol
T
T
T
T
T
HD:DAT
SU:STO
T
HD:STA
SU:STA
SU:DAT
T
T
T
DSU
BUF
high
low
T
SU:STO
CY7C68310
T
BUF
5066 ns
5066 ns
5066 ns
5066 ns
5066 ns
5066 ns
5066 ns
5066 ns
500 ns
Value
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