CY7C68310 CYPRESS [Cypress Semiconductor], CY7C68310 Datasheet - Page 16

• Manufacturer Part Number: CY7C68310
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 6-2. EEPROM Organization (continued)
Document 38-08030 Rev. *H
0x0A
0x0B
Address
I
2
C
Reserved
SRST Enable
ATA Data Assert
ATA Data Recover
ATA Data Set-up
Drive Power Valid Polarity
Override PIO Timing
Drive Power Valid Enable
Field Name
Bits (6:1) – must be set to ‘0’.
Bit (0)
Soft-reset during drive initialization.
‘0’ = Disable soft-reset functionality
‘1’ = Enable soft-reset during drive initialization
Bits (7:4)
ATA cycle times are calculated using Data Assert and Data
Recover values.
Standard values for ATA-compliant devices and a 30.0-MHz
system clock (in binary):
mode 0
mode 1
mode 2
mode 3
mode 4
Bits (3:0)
Standard recover values and cycle times for ATA-compliant
devices and a 30.0 MHz system clock (in binary):
mode 0
mode 1
mode 2
mode 3
mode 4
Bits (7:5)
Set-up time is only incurred on the first data cycle of a burst.
Standard values for ATA-compliant devices and a 30.0 MHz
system clock are (in binary):
mode 0
mode 1
mode 2
mode 3
mode 4
Bit (4)
Controls the polarity of DRVPWRVLD pin.
‘0’ = Active LOW (“connector ground” indication)
‘1’ = Active HIGH (power indication from device)
Bit (3)
This field is used in conjunction with ATA Data Set-up, ATA
Data Assertion, ATA Data Recover, and PIO Mode Selection
fields.
‘0’ = Use timing information acquired from the Drive
‘1’ = Override device timing information with configuration
values
Bit (2)
0101
0011
0011
0010
0010
1100
0111
0011
0010
0000
010
001
001
001
000
(2+1)*33.33 = 133 ns
(1+1)*33.33 = 66 ns
(1+1)*33.33 = 66 ns
(1+1)*33.33 = 66 ns
(0+1)*33.33 = 33 ns
Field Description
(3+1)+(7+1)*33.33 = 400 ns
(3+1)*33.33 = 133 ns
(3+1)*33.33 = 133 ns
(4+1)+(12+1)*33.33 = 600 ns
(2+1)+(3+1)*33.33 = 233 ns
(5+1)*33.33 = 200 ns
(2+1)*33.33 = 100 ns
(2+1)*33.33 = 100 ns
(2+1)+(2+1)*33.33 = 200 ns
(2+1)+(0+1)*33.33 = 133 ns
Required
I
2
C Data
CY7C68310
Page 16 of 34
Example
I
2
C Data
0x20
0x00