CY7C1470BV33-200AXI CYPRESS [Cypress Semiconductor], CY7C1470BV33-200AXI Datasheet - Page 15

• Manufacturer Part Number: CY7C1470BV33-200AXI
• Description: 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

TAP AC Switching Characteristics
Over the Operating Range
Notes
Document #: 001-15031 Rev. *C
Clock
t
t
t
t
Output Times
t
t
Setup Times
t
t
t
Hold Times
t
t
t
9. t
10. Test conditions are specified using the load in TAP AC Test Conditions. t
Parameter
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
[9, 10]
Description
R
/t
F
= 1 ns.
CY7C1472BV33, CY7C1474BV33
Min
50
20
20
5
5
5
0
5
5
5
CY7C1470BV33
Max
20
10
Page 15 of 30
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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