CY7C1470BV33-200AXI CYPRESS [Cypress Semiconductor], CY7C1470BV33-200AXI Datasheet - Page 11

• Manufacturer Part Number: CY7C1470BV33-200AXI
• Description: 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 5. Partial Write Cycle Description
The partial write cycle description for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows.
Document #: 001-15031 Rev. *C
Read
Write – No bytes written
Write Byte a – (DQ
Write Byte b – (DQ
Write Bytes b, a
Write Byte c – (DQ
Write Bytes c, a
Write Bytes c, b
Write Bytes c, b, a
Write Byte d – (DQ
Write Bytes d, a
Write Bytes d, b
Write Bytes d, b, a
Write Bytes d, c
Write Bytes d, c, a
Write Bytes d, c, b
Write All Bytes
Read
Write – No Bytes Written
Write Byte a – (DQ
Write Byte b – (DQ
Write Both Bytes
Read
Write – No Bytes Written
Write Byte X − (DQ
Write All Bytes
Note
8. Table lists only a partial listing of the Byte Write combinations. Any combination of BW
Function (CY7C1470BV33)
c
a
b
d
a
b
x
and DQP
Function (CY7C1472BV33)
Function (CY7C1474BV33)
and DQP
and DQP
and DQP
and DQP
and DQP
and DQP
c
a
d
a
b
x)
b
)
)
)
)
)
)
WE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
[a:d]
BW
is valid. Appropriate Write is based on which Byte Write is active.
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
CY7C1472BV33, CY7C1474BV33
d
WE
H
L
L
L
L
WE
BW
H
L
L
L
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
c
BW
H
H
L
L
x
b
[1, 2, 3, 8]
BW
CY7C1470BV33
H
H
H
H
H
H
H
X
H
L
L
L
L
L
L
L
L
b
All BW = L
BW
BW
H
H
H
x
L
L
x
L
Page 11 of 30
BW
a
x
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
a
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