CY7C1470BV33-200AXI CYPRESS [Cypress Semiconductor], CY7C1470BV33-200AXI Datasheet
CY7C1470BV33-200AXI
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CY7C1470BV33-200AXI Summary of contents
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... Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle ...
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... Logic Block Diagram – CY7C1470BV33 (2M x 36) A0, A1, A MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ CE1 CE2 CE3 ZZ Logic Block Diagram – CY7C1472BV33 (4M x 18) A0, A1, A MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ ...
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... REGISTER BURST A0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 WRITE REGISTRY MEMORY AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS INPUT E REGISTER 1 READ LOGIC Sleep Control CY7C1470BV33 ...
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... DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1470BV33 DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa ...
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... DDQ DDQ DDQ N DQP DDQ P NC/144M MODE A Document #: 001-15031 Rev. *C CY7C1472BV33, CY7C1474BV33 CY7C1470BV33 ( CEN CLK ...
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... DDQ DDQ MODE TDI CY7C1470BV33 DQb DQb 3 BWS BWS DQb DQb b f BWS BWS DQb DQb DQb DQb DQPf DQPb DDQ DDQ ...
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... The outputs are automat controlled DQP is controlled controlled DQP is controlled DQP is controlled CY7C1470BV33 and DQP , BW controls DQ and DQP controls DQ and DQP , controls DQ and DQP . ...
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... During normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull-down. Functional Overview The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are synchronous-pipelined Burst NoBL SRAMs designed specif- ically to eliminate wait states during read or write transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock ...
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... OE. Burst Write Accesses The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 has an on-chip burst counter that enables the user to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in “ ...
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... Table 4. Truth Table The truth table for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows. Operation Address Used Deselect Cycle None Continue None Deselect Cycle Read Cycle External (Begin Burst) Read Cycle Next (Continue Burst) NOP/Dummy Read External (Begin Burst) Dummy Read Next (Continue Burst) ...
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... Table 5. Partial Write Cycle Description The partial write cycle description for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows. Function (CY7C1470BV33) Read Write – No bytes written Write Byte a – (DQ and DQP ) a a Write Byte b – (DQ and DQP ) b b Write Bytes b, a Write Byte c – (DQ ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... TAP controller’s capture setup plus hold time (t plus The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue still CY7C1470BV33 Page [+] Feedback ...
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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Figure 4. TAP Timing TDIS t TDIH t TDOX DON’ UNDEFINED CY7C1470BV33 TDOV Page [+] Feedback ...
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... CS CH 10. Test conditions are specified using the load in TAP AC Test Conditions. t Document #: 001-15031 Rev. *C CY7C1472BV33, CY7C1474BV33 Description / ns CY7C1470BV33 Min Max Unit MHz ...
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... OH DDQ V = 2.5V DDQ 3.3V OL DDQ 2.5V OL DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1470BV33 to 2.5V SS 1.25V 50Ω 50Ω 20pF O Min Max Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 –0.3 0.8 V –0.3 0.7 V –5 5 µ ...
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... Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. CY7C1470BV33 Description Describes the version number Reserved for internal use ...
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... J10 R8 30 H11 P3 31 G11 P4 32 F11 P8 33 E11 P9 34 D11 P10 35 C11 R9 36 A11 R10 37 A9 R11 38 B9 M10 39 A10 CY7C1470BV33 Bit # 165-Ball Bit # 165-Ball ID 40 B10 ...
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... U6 74 H10 W7 75 G11 V7 76 G10 U7 77 F11 V8 78 F10 V9 79 E10 W11 80 E11 W10 81 D11 V11 82 D10 V10 83 C11 U11 84 C10 CY7C1470BV33 Bit # 209-Ball ID 85 B11 86 B10 87 A11 88 A10 ...
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... Device Deselected, All speed grades DD ≤ 0. − 0.3V, > DDQ /2). Undershoot: V (AC)> –2V (pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1470BV33 + 0.5V DD Ambient DDQ Temperature 0°C to +70°C 3.3V 2.5V – 5% –5%/+10 Min Max Unit 3 ...
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... OUTPUT DDQ GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND (b) SCOPE CY7C1470BV33 Min Max Unit 245 mA 245 mA 245 mA 135 mA 100 TQFP 165 FBGA 209 FBGA Unit Max Max Max ...
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... DD “AC Test Loads and Waveforms” on page and t is less than t to eliminate bus contention between SRAMs when sharing the same data EOLZ CHZ CLZ CY7C1470BV33 = 2.5V. Test conditions shown in DDQ –200 –167 Unit Min Max Min ...
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... DOH CLZ D(A1) D(A2) D(A2+1) Q(A3) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1470BV33 OEV CHZ Q(A4) Q(A4+1) D(A5) Q(A6) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH Page ...
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... A3 A4 D(A1) Q(A2) Q(A3) READ WRITE STALL Q(A3) D(A4) DON’T CARE [24, 25] Figure 7. ZZ Mode Timing High-Z DON’T CARE “Truth Table” on page 10 for all possible signal conditions to deselect the device. CY7C1470BV33 CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT UNDEFINED t ZZREC t RZZI ...
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... CY7C1470BV33-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Pb-free CY7C1472BV33-200BZXC CY7C1474BV33-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1474BV33-200BGXC CY7C1470BV33-200AXI 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-free CY7C1472BV33-200AXI CY7C1470BV33-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) ...
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... Thin Quad Flat Pack ( 1.4 mm) Pb-free CY7C1472BV33-250AXC CY7C1470BV33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1472BV33-250BZC CY7C1470BV33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Pb-free CY7C1472BV33-250BZXC CY7C1474BV33-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1474BV33-250BGXC CY7C1470BV33-250AXI 51-85050 100-pin Thin Quad Flat Pack ( ...
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... JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1470BV33 1.40±0.05 12°±1° A SEE DETAIL (8X) ...
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... SEATING PLANE C Document #: 001-15031 Rev. *C CY7C1472BV33, CY7C1474BV33 0.15(4X) CY7C1470BV33 PIN 1 CORNER BOTTOM VIEW Ø0. Ø0. Ø0.45±0.05(165X ...
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... Package Diagrams (continued) Figure 10. 209-Ball FBGA ( 1.76 mm), 51-85167 Document #: 001-15031 Rev. *C CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 51-85167-** Page [+] Feedback ...
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... Document History Page Document Title: CY7C1470BV33/CY7C1472BV33/CY7C1474BV33, 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 001-15031 Orig. of REV. ECN No. Issue Date Change ** 1032642 See ECN VKN/KKVTMP New Data Sheet *A 1897447 See ECN VKN/AESA *B 2082487 See ECN *C 2159486 See ECN VKN/PYRS © ...