CY7C144AV CYPRESS [Cypress Semiconductor], CY7C144AV Datasheet - Page 9

• Manufacturer Part Number: CY7C144AV
• Description: 3.3V 8K/16K x 8 Dual-Port Static RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Document #: 38-06051 Rev. *E
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes
HD
HZWE
LZWE
WDD
DDD
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
INS
INR
SOP
SWRD
SPS
SAA
13. Test conditions used are Load 3.
14. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy
15. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
16. Test conditions used are Load 2.
17. t
BUSY TIMING
INTERRUPT TIMING
SEMAPHORE TIMING
waveform.
Parameter
BDD
[17]
[15]
[15]
[13, 14]
[13, 14]
is a calculated parameter and is the greater of t
[16]
Data hold from write end
R/W LOW to High Z
R/W HIGH to Low Z
Write pulse to data delay
Write data valid to read data valid
BUSY LOW from address match
BUSY HIGH from address mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port set-up for priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to data valid
INT set time
INT reset time
SEM flag update pulse (OE or SEM)
SEM flag write to read time
SEM flag contention window
SEM address access time
[16]
Over the Operating Range
Description
WDD
–t
PWE
(actual) or t
DDD
–t
SD
(actual).
[8]
(continued)
Min
17
12
0
–
3
–
–
–
–
–
–
5
0
–
–
–
5
5
–
CY7C144AV
CY7C006AV
-25
Max
15
50
35
20
17
25
25
20
20
20
20
–
–
–
–
–
–
–
CY7C144AV
CY7C006AV
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 9 of 21
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