CY7C144AV CYPRESS [Cypress Semiconductor], CY7C144AV Datasheet

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CY7C144AV

Manufacturer Part Number
CY7C144AV
Description
3.3V 8K/16K x 8 Dual-Port Static RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

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Features
Cypress Semiconductor Corporation
Document #: 38-06051 Rev. *E
Notes
True dual-ported memory cells which allow
simultaneous access of the same memory location
8K/16K x 8 organizations
(CY7C144AV/006AV)
0.35-micron complementary metal oxide semiconductor
(CMOS) for optimum speed/power
High-speed access: 25 ns
Low operating power
Fully asynchronous operation
Automatic power-down
1. I/O
2. A
3. BUSY is an output in master mode and an input in slave mode.
CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 8K/16K x 8
Dual-Port Static RAM
— Active: I
— Standby: I
Logic Block Diagram
A
A
CE
OE
R/W
SEM
BUSY
INT
R/W
CE
OE
I/O
0L
0L
0
–A
0
L
L
0L
L
L
–A
–A
L
–I/O
L
L
12
L
–I/O
[2]
[2]
L
12–13L
12–13L
for 8K devices; A
7
[3]
for x8 devices
CC
7L
[1]
SB3
= 115 mA (typical)
= 10 A (typical)
0
13–14
–A
8
13
for 16K devices
Address
Decode
13–14
198 Champion Court
Control
I/O
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
Expandable data bus to 16 bits or more using Master/ Slave
chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Pin select for Master or Slave
Commercial and industrial temperature ranges
Available in 64-pin thin quad flat pack (TQFP) (7C006AV &
7C144AV)
Pb-free packages available
Control
I/O
San Jose
Dual-Port Static RAM
Address
Decode
,
13–14
CA 95134-1709
3.3V 8K/16K x 8
13–14
8
Revised February 4, 2011
CY7C144AV
CY7C006AV
A
A
I/O
0R
0R
[3]
0R
–A
–A
408-943-2600
BUSY
–I/O
12–13R
12–13R
[2]
[2]
SEM
R/W
R/W
[1]
INT
CE
OE
OE
CE
7R
R
R
R
R
R
R
R
R
R
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Related parts for CY7C144AV

CY7C144AV Summary of contents

Page 1

... CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 8K/16K x 8 Dual-Port Static RAM Features True dual-ported memory cells which allow ■ simultaneous access of the same memory location 8K/16K x 8 organizations ■ (CY7C144AV/006AV) 0.35-micron complementary metal oxide semiconductor ■ (CMOS) for optimum speed/power High-speed access ■ ...

Page 2

... Document #: 38-06051 Rev. *E Data Retention Mode ...................................................... 10 Timing .............................................................................. 10 Switching Waveforms .................................................... 11 Ordering Information ...................................................... 18 Ordering Code Definition ........................................... 18 Package Diagrams .......................................................... 19 Acronyms ........................................................................ 19 Document Conventions ................................................. 19 Units of Measure ....................................................... 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 21 Worldwide Sales and Design Support ....................... 21 Products .................................................................... 21 PSoC Solutions ......................................................... 21 CY7C144AV CY7C006AV Page [+] Feedback ...

Page 3

... CC GND I/O 0R I I/O 3R I/O 4R I/O 5R Document #: 38-06051 Rev. *E 64-Pin TQFP Top View CY7C144AV ( CY7C144AV CY7C006AV INT L BUSY L GND M/S BUSY ...

Page 4

... CY7C144AV CY7C006AV INT L 42 BUSY L GND 41 M BUSY R 38 INT CY7C144AV CY7C006AV -25 25 115 30 10 A Page [+] Feedback ...

Page 5

... Architecture The CY7C144AV and CY7C006AV and consist of an array of 8K and 16K words of 8 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port ...

Page 6

... If both ports attempt to access the semaphore within t of each other, the semaphore will definitely be obtained by one is used zero is 0 side or the other, but there is no guarantee which side will control the semaphore. CY7C144AV CY7C006AV Table 3 shows sample semaphore SPS Page ...

Page 7

... MHz 3 CY7C144AV CY7C006AV Ambient Temperature V CC   3.3 V  300 +70 C   3.3 V  300 mV – +85 C CY7C144AV CY7C006AV -25 Unit Typ Max – V 0.4 V – V 0.8 V A 10 115 165 mA – – mA ...

Page 8

... HZCE LZCE HZOE CY7C144AV CY7C006AV 3 590  OUTPUT 435  (c) Three-State Delay (Load 2) (Used for & HZWE LZWE including scope and jig) Unit ...

Page 9

... Min 0 – 3 – – – – – – – – – – –t (actual –t (actual). WDD PWE DDD SD CY7C144AV CY7C006AV CY7C144AV CY7C006AV Unit -25 Max – – ns – ns – ...

Page 10

... Data Retention Mode The CY7C144AV and CY7C006AV are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, within – 0 ...

Page 11

... To access semaphore Document #: 38-06051 Rev DATA VALID t ACE t DOE t LZOE t LZCE [19, 21, 22, 23 LZCE t ABE t ACE t LZCE , SEM = CY7C144AV CY7C006AV [19, 20, 21] t OHA [19, 22, 23] t HZCE t HZOE DATA VALID OHA t HZCE Page [+] Feedback ...

Page 12

... [27] t PWE [28] t HZWE SCE LOW CE or SEM PWE CY7C144AV CY7C006AV [24, 25, 26, 27] [28] t HZOE LZWE Note [24, 25, 26, 31 allow the I/O drivers to turn off and data HZWE SD Page ...

Page 13

... Document #: 38-06051 Rev SAA VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE MATCH t SPS MATCH = CE = HIGH CY7C144AV CY7C006AV [32] t OHA t ACE DATA VALID OUT t DOE [33, 34, 35] Page [+] Feedback ...

Page 14

... ADDRESS L BUSY L DATA OUTL Figure 9. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 36 LOW Document #: 38-06051 Rev MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C144AV CY7C006AV [36 BHA t BDD t DDD VALID Page [+] Feedback ...

Page 15

... BUSY will be asserted. PS Document #: 38-06051 Rev. *E ADDRESS MATCH BLC ADDRESS MATCH BLC ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C144AV CY7C006AV [37] t BHC t BHC [37] Page [+] Feedback ...

Page 16

... INS INR L Document #: 38-06051 Rev. *E Figure 12. Interrupt Timing Diagrams t WC [38 READ 1FFF/3FFF (See Functional Description) [39] t INR t WC [38 READ 1FFE/3FFE (See Functional Description) [39] t INR ) is deasserted first R asserted last. L CY7C144AV CY7C006AV Page [+] Feedback ...

Page 17

... Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C144AV CY7C006AV Operation Right Port 0R–13R [40 1FFF/3FFF [40] ...

Page 18

... Pb-free Thin Quad Flat Pack Package Name Package Type A65 64-Pin Pb-free Thin Quad Flat Pack Operating Range Commercial X:Pb-free (RoHS compliant) Package: TQFP Speed grade: 25ns V/AV : 3.3 V Part Identifier Dual port SRAM Company Id: CY=Cypress CY7C144AV CY7C006AV Operating Range Commercial Operating Range Commercial Page [+] Feedback ...

Page 19

... Units of Measure Symbol Unit of Measure °C degrees Celsius A microamperes mA milliampere MHz megahertz ns nanoseconds pF picofarads V volts  ohms W watts All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-06051 Rev. *E CY7C144AV CY7C006AV 51-85046 *E Page [+] Feedback ...

Page 20

... Document History Page Document Title: CY7C144AV/CY7C006AV 3.3V 8K/16K x 8 Dual-Port Static RAM Document Number: 38-06051 REV. ECN NO. Issue Date Change ** 110203 12/02/01 *A 122301 12/27/02 *B 237623 See ECN *C 373615 See ECN *D 2896210 03/22/2010 *E 3161515 02/04/2011 Document #: 38-06051 Rev. *E Orig. of Description of Change SZV Change from Spec number: 38-00837 to 38-06051 ...

Page 21

... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06051 Rev. *E All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised February 4, 2011 CY7C144AV CY7C006AV PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...

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