CY7C144AV CYPRESS [Cypress Semiconductor], CY7C144AV Datasheet - Page 5

• Manufacturer Part Number: CY7C144AV
• Description: 3.3V 8K/16K x 8 Dual-Port Static RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Architecture
The CY7C144AV and CY7C006AV and consist of an array of 8K
and 16K words of 8 bits each of dual-port RAM cells, I/O and
address lines, and control signals (CE, OE, R/W). These control
pins permit independent access for reads or writes to any
location in memory. To handle simultaneous writes/reads to the
same location, a BUSY pin is provided on each port. Two
interrupt (INT) pins can be utilized for port-to-port communi-
cation. Two semaphore (SEM) control pins are used for
allocating shared resources. With the M/S pin, the device can
function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). The device also has an automatic
power-down feature controlled by CE. Each port is provided with
its own output enable control (OE), which allows data to be read
from the device.
Functional Description
The CY7C144AV and CY7C006AV are low-power CMOS
8K/16K x 8 dual-port static RAMs. Various arbitration schemes
are included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can be
utilized as standalone 8-bit dual-port static RAMs or multiple
devices can be combined in order to function as a 16-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a Chip Select (CE) pin.
Read and Write Operations
When writing data must be set up for a duration of t
rising edge of R/W in order to guarantee a valid write. A write
operation is controlled by either the R/W pin (see Write Cycle No.
1 waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summarized
in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port t
after the data is presented on the other port.
When reading the device, the user must assert both the OE and
CE pins. Data will be available t
Document #: 38-06051 Rev. *E
logic.
Application
ACE
after CE or t
areas
DOE
SD
after OE is
before the
include
DDD
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (1FFF for the
CY7C144AV and 3FFF for the CY7C006AV) is the mailbox for
the right port and the second-highest memory location (1FFE for
the CY7C144AV and 3FFE for the CY7C006AV) is the mailbox
for the left port. When one port writes to the other port’s mailbox,
an interrupt is generated to the owner. The interrupt is reset when
the owner reads the contents of the mailbox. The message is
user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it. If an application
does not require message passing, do not connect the interrupt
pin to the processor’s interrupt request input pin. The operation
of the interrupts and their interaction with Busy are summarized
in
Busy
The CY7C144AV and CY7C006AV provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
both ports’ CEs are asserted and an address match occurs within
t
access. If t
to the location, but it is not predictable which port will get that
permission. BUSY will be asserted t
or t
Master/Slave
An M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
This will allow the device to interface to a master device with no
external components. Writing to slave devices must be delayed
until after the BUSY input has settled (t
the slave chip may begin a write cycle during a contention
situation. When tied HIGH, the M/S pin allows the device to be
used as a master and, therefore, the BUSY line is an output.
BUSY can then be used to send the arbitration outcome to a
slave.
Semaphore Operation
The CY7C144AV and CY7C006AV provide eight semaphore
latches, which are separate from the dual-port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports. The state of the semaphore indicates that
a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
be deasserted for t
The semaphore value will be available t
rising edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource,
otherwise (reads a one) it assumes the right port has control and
PS
Table
BLC
of each other, the busy logic will determine which port has
after CE is taken LOW.
2.
PS
is violated, one port will definitely gain permission
SOP
before attempting to read the semaphore.
BLA
BLC
after an address match
SWRD
CY7C144AV
CY7C006AV
or t
+ t
BLA
DOE
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), otherwise,
after the
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