CY7C144AV CYPRESS [Cypress Semiconductor], CY7C144AV Datasheet - Page 12

• Manufacturer Part Number: CY7C144AV
• Description: 3.3V 8K/16K x 8 Dual-Port Static RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Document #: 38-06051 Rev. *E
Notes
CE
24. R/W must be HIGH during all address transitions.
25. A write occurs during the overlap (t
26. t
27. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
28. Transition is measured 500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
29. To access RAM, CE = V
30. During this period, the I/O pins are in the output state, and input signals must not be applied.
31. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
to be placed on the bus for the required t
as short as the specified t
[29]
HA
[29]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
R/W
R/W
OE
IL
PWE
, SEM = V
.
t
t
SA
SA
Figure 4. Write Cycle No. 1: R/W Controlled Timing
Figure 5. Write Cycle No. 2: CE Controlled Timing
(continued)
SCE
IH
Note 30
.
or t
SD
PWE
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
) of a LOW CE or SEM.
t
HZWE
[28]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[27]
t
t
SD
SD
PWE
or (t
HZWE
t
t
HA
HA
[24, 25, 26, 31]
[24, 25, 26, 27]
t
t
+ t
HD
HD
t
SD
LZWE
) to allow the I/O drivers to turn off and data
t
HZOE
[28]
Note 30
CY7C144AV
CY7C006AV
Page 12 of 21
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