M29W640GB NUMONYX [Numonyx B.V], M29W640GB Datasheet - Page 19

• Manufacturer Part Number: M29W640GB
• Description: 64 Mbit (8Mb x8 or 4Mb x16, Page) 3V supply Flash memory
• Manufacturer: NUMONYX [Numonyx B.V]

M29W640GH, M29W640GL, M29W640GT, M29W640GB
3
3.1
3.2
3.3
3.4
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See
= V
than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus
operations.
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
Enable High, V
ac waveforms (8-bit
output becomes valid.
Bus Write
Bus Write operations write to the Command Interface. To speed up the read operation the
memory array can be read in Page mode where data is internally read and stored in a page
buffer. The Page has a size of 4 words and is addressed by the address inputs A0-A1.
A valid Bus Write operation begins by setting the desired address on the Address Inputs.
The Address Inputs are latched by the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the
Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs
first. Output Enable must remain High, V
Figure 15: Write ac waveforms, Write Enable Controlled (8-bit
waveforms, Chip Enable Controlled (8-bit
Table 19: Write ac
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V
Standby
When Chip Enable is High, V
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, I
Standby current level see
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I
IL
and
Table 8: Bus Operations, BYTE = V
IH
. The Data Inputs/Outputs will output the value, see
CC3
characteristics, for details of the timing requirements.
mode), and
, for Program or Erase operations until the operation completes.
Table 17: DC
IH
CC2
, the memory enters Standby mode and the Data
IL
Table 18: Read ac
, to Chip Enable and Output Enable and keeping Write
, Chip Enable should be held within V
characteristics.
IH
mode), and
, during the whole Bus Write operation. See
IH
, for a summary. Typically glitches of less
characteristics, for details of when the
Table 19: Write ac characteristics
Table 7: Bus Operations, BYTE
mode),
Figure 13: Read Mode
Figure 16: Write ac
CC
± 0.2V. For the
Bus operations
19/90
and
IH
.