MT4C1M16C3 MICRON [Micron Technology], MT4C1M16C3 Datasheet - Page 9

• Manufacturer Part Number: MT4C1M16C3
• Description: FPM DRAM
• Manufacturer: MICRON [Micron Technology]

NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. V
9. In addition to meeting the transition rate
10. If CAS# = V
11. If CAS# = V
12. Measured with a load equivalent to two TTL
13. If CAS# is LOW at the falling edge of RAS#, Q will
14. The
15. The
16. Either
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
f = 1 MHz.
values are obtained with minimum cycle time
and the output open.
indicate cycle time at which proper operation
over the full temperature range (0°C ≤ T
for commercial and (-20°C ≤ T
extended “ET” is ensured.
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR), before proper device operation is
ensured. The eight RAS# cycle wake-ups should
be repeated any time the
ment is exceeded.
measuring timing of input signals. Transition
times are measured between V
between V
specification, all input signals must transit
between V
monotonic manner.
the last valid READ cycle.
gates, 100pF and V
be maintained from the previous cycle. To
initiate a new cycle and clear the Q buffer, CAS#
must be pulsed HIGH for
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively
by
without the
always be met.
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively
by
without the
t
cycle.
RCD was greater than the specified
RAD was greater than the specified
CAC must always be met.
CC
IH
t
t
AA (
is dependent on output loading. Specified
(MIN) and V
CAC (
t
t
RCD (MAX) limit is no longer specified.
RAD (MAX) limit is no longer specified.
t
RCH or
t
RAC and
t
RAC [MIN] no longer applied). With or
IL
IH
IH
IL
t
t
and V
, data output may contain data from
and V
RAD (MAX) limit,
RCD limit,
, data output is High-Z.
t
RRH must be satisfied for a READ
IL
t
(MAX) are reference levels for
IH
CAC no longer applied). With or
IL
OL
).
(or between V
= 0.8V and V
t
AA and
t
t
t
REF refresh require-
CP.
T = 5ns.
SS
CC
.
A
IH
t
AA,
= +3.3V or 5.0V;
≤ 80°C) for
t
and V
CAC must
OH
IL
t
RAC, and
and V
= 2V.
t
t
RAD (MAX)
RCD (MAX)
IL
A
(or
IH
≤ 70°C)
) in a
t
t
RAD
RCD
9
17.
18.
19. These parameters are referenced to CAS# leading
20. During a READ cycle, if OE# is LOW then taken
21. A HIDDEN REFRESH may also be performed
22. All other inputs at 0.2V or V
23. Column address changed once each cycle.
24. LATE WRITE and READ-MODIFY-WRITE cycles
25. The DQs open during READ cycles once
26. The 3ns minimum is a parameter guaranteed by
27. The first CASx edge to transition LOW.
28. The last CASx edge to transition HIGH.
29. Output parameter (DQx) is referenced to
30. Last falling CASx edge to first rising CASx edge.
31. Last rising CASx edge to next cycle’s last rising
t
achieves the open circuit condition; it is not a
reference to V
t
operating parameters in LATE WRITE and READ-
MODIFY-WRITE cycles only. If
(MIN), the cycle is an EARLY WRITE cycle and the
data out-put will remain an open circuit through-
out the entire cycle. If
t
the cycle is a READ WRITE and the data output
will contain data read from the selected cell. If
neither of the above conditions is met, the state
of Q (at access time and until CAS# or OE# goes
back to V
WE# taken LOW after CAS# goes LOW result in a
LATE WRITE (OE#-controlled) cycle.
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
HIGH before CAS# goes HIGH, Q goes open. If
OE# is tied permanently LOW, LATE WRITE and
READ-MODIFY-WRITE operations are not
permissible and should not be attempted.
after a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
must have both
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. The DQs will provide the previously read
data if CAS# remains LOW and OE# is taken back
LOW after
to OE# going back LOW, the DQs will remain
open.
t
design.
corresponding CAS# input; DQ0-DQ7 by CASL#
and DQ8-DQ15 by CASH#.
CASx edge.
OFF (MAX) defines the time at which the output
WCS,
AWD ≥
OFF occur.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RWD,
t
AWD (MIN) and
IH
t
) is indeterminate. OE# held HIGH and
OEH is met. If CAS# goes HIGH prior
t
OH
AWD, and
t
or V
OD and
OL
t
.
RWD ≥
t
t
t
CWD are restrictive
CWD ≥
OEH met (OE# HIGH
CC
- 0.2V.
1 MEG x 16
FPM DRAM
t
t
RWD (MIN),
WCS ≥
t
CWD (MIN),
©2001, Micron Technology, Inc.
t
WCS
t
OD or