MT4C1M16C3 MICRON [Micron Technology], MT4C1M16C3 Datasheet - Page 4

• Manufacturer Part Number: MT4C1M16C3
• Description: FPM DRAM
• Manufacturer: MICRON [Micron Technology]

mode of operation if both bytes are active. A CAS#
precharge must be satisfied prior to changing modes of
operation between the upper and lower bytes. For ex-
ample, an EARLY WRITE on one byte and a LATE WRITE
on the other byte are not allowed during the same cycle.
However, an EARLY WRITE on one byte and a LATE
WRITE on the other byte, after a CAS# precharge has
been satisfied, are permissible.
DRAM REFRESH
power and executing any RAS# cycle (READ, WRITE) or
RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN)
so that all 1,024 combinations of RAS# addresses are
executed within
The CBR and EXTENDED and SELF REFRESH cycles
will invoke the internal refresh counter for automatic
RAS# addressing.
version. The self refresh feature is initiated by per-
forming a CBR REFRESH cycle and holding RAS# LOW
for the specified
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
Additionally, both bytes must always be of the same
Preserve correct memory cell data by maintaining
An optional self refresh mode is available on the “S”
t
t
RASS. The “S” option allows the user
REF (MAX), regardless of sequence.
LOWER BYTE
UPPER BYTE
(DQ8-DQ15)
(DQ0-DQ7)
OF WORD
OF WORD
CASH#
CASL#
RAS#
WE#
STORED
Z = High-Z
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
WORD and BYTE READ Example
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
ADDRESS 0
WORD READ
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
Figure 2
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
4
STORED
DATA
the choice of a fully static, low-power data retention
mode or a dynamic refresh mode at the extended re-
fresh period of 128ms, or 125µs per row, when using a
distributed CBR REFRESH. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.
RAS# HIGH for a minimum time of
allows for the completion of any internal refresh cycles
that may be in process at the time of the RAS# LOW-
to-HIGH transition. If the DRAM controller uses a dis-
tributed CBR refresh sequence, a burst refresh is not
required upon exiting self refresh. However, if the
DRAM controller utilizes a RAS#-ONLY or burst CBR
refresh sequence, all 1,024 rows must be refreshed us-
ing a minimum
mal operation.
STANDBY
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
0
1
0
1
0
0
0
0
1
1
0
1
1
1
1
1
The self refresh mode is terminated by driving
Returning RAS# and CAS# HIGH terminates a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
LOWER BYTE READ
OUTPUT
DATA
ADDRESS 1
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
t
RC refresh rate prior to resuming nor-
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
1 MEG x 16
FPM DRAM
t
RPS. This delay
©2001, Micron Technology, Inc.