MT4C1M16C3 MICRON [Micron Technology], MT4C1M16C3 Datasheet - Page 2

• Manufacturer Part Number: MT4C1M16C3
• Description: FPM DRAM
• Manufacturer: MICRON [Micron Technology]

GENERAL DESCRIPTION (continued)
the last CAS# to transition back HIGH. Use of only one
of the two results in a BYTE access cycle. CASL#
transitioning LOW selects an access cycle for the lower
byte (DQ0-DQ7), and CASH# transitioning LOW se-
lects an access cycle for the upper byte (DQ8-DQ15).
dress bits during READ or WRITE cycles. These are
entered ten bits (A0-A9) at a time. RAS# is used to latch
the first ten bits and CAS# the latter ten bits. The CAS#
function is determined by the first CAS# (CASL# or
CASH#) to transition LOW and the last one to transition
back HIGH. The CAS# function also determines
whether the cycle will be a refresh cycle (RAS#-ONLY)
or an active cycle (READ, WRITE, or READ-WRITE) once
RAS# goes LOW.
CAS# signal that functions identically to a single CAS#
input on other DRAMs. The key difference is that each
CAS# input (CASL# and CASH#) controls its corre-
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
RAS#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Each bit is uniquely addressed through the 20 ad-
The CASL# and CASH# inputs internally generate a
CASH#
CASL#
WE#
10
10
CONTROLLER
BUFFERS (10)
NO. 2 CLOCK
NO. 1 CLOCK
GENERATOR
GENERATOR
COLUMN-
COUNTER
ADDRESS
ADDRESS
REFRESH
REFRESH
BUFFER
ROW-
10
CAS#
FUNCTIONAL BLOCK DIAGRAM
10
2
10
sponding DQ tristate logic (in conjunction with OE#
and WE#). CASL# controls DQ0-DQ7 and CASH# con-
trols DQ8-DQ15. The two CAS# controls give the
1 Meg x 16 DRAM BYTE WRITE cycle capabilities.
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE#
or CAS, whichever occurs last. Taking WE# LOW will
initiate a WRITE cycle, selecting DQ0-DQ15. If WE#
goes LOW prior to CAS# going LOW, the output pin(s)
remain open (High-Z) until the next CAS# cycle. If WE#
goes LOW after CAS# goes LOW and data reaches the
output pins, data-out (Q) is activated and retains the
selected cell data as long as CAS# and OE# remain LOW
(regardless of WE# or RAS#). This late WE# pulse re-
sults in a READ-WRITE cycle.
through 16 pins using common I/O. Pin direction is
controlled by OE# and WE#.
1,024
A logic HIGH on WE# dictates read mode, while a
The 16 data inputs and 16 data outputs are routed
DECODER
COLUMN
1,024
SENSE AMPLIFIERS
1,024 x 1,024 x 16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I/O GATING
MEMORY
DATA-IN BUFFER
1,024 x 16
ARRAY
16
DATA-OUT
BUFFER
16
1 MEG x 16
FPM DRAM
©2001, Micron Technology, Inc.
16
DQ15
OE#
DQ0
V
V
DD
SS