MT4C1M16C3 MICRON [Micron Technology], MT4C1M16C3 Datasheet - Page 20

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MT4C1M16C3

Manufacturer Part Number
MT4C1M16C3
Description
FPM DRAM
Manufacturer
MICRON [Micron Technology]
Datasheet

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TIMING PARAMETERS
NOTE: 1. Once
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
SYMBOL
t
t
t
t
t
CHD
CLCH
CP
CSR
RASS
RAS#
CAS#
WE#
DQ
V
V
2. Once
V
V
V
V
V
V
OH
OL
IH
IL
IH
IL
IH
IL
MIN
100
15
10
8
5
t
t
RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.
RPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used.
t RP
t RPC
t CP
-5
MAX
t WRP
t CSR
MIN
100
t RASS
t CHD
t WRH
15
10
5
5
(Addresses and OE# = DON’T CARE)
-6
(
(
MAX
(
(
(
)
(
(
)
)
)
)
)
)
(
(
)
)
(
(
(
(
(
)
)
)
)
)
SELF REFRESH CYCLE
OPEN
UNITS
ns
ns
ns
ns
µs
20
SYMBOL
t
t
t
t
t
RP
RPC
RPS
WRH
WRP
NOTE 1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN
30
90
5
8
8
t RPC
t RPS
-5
t CP
t WRP
MAX
t WRH
MIN
105
NOTE 2
40
10
10
5
(
1 MEG x 16
)
FPM DRAM
(
)
-6
©2001, Micron Technology, Inc.
DON’T CARE
UNDEFINED
MAX
UNITS
ns
ns
ns
ns
ns

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