MT48LC128M4A2_07 MICRON [Micron Technology], MT48LC128M4A2_07 Datasheet - Page 48

• Manufacturer Part Number: MT48LC128M4A2_07
• Description: 512Mb x4, x8, x16 SDRAM
• Manufacturer: MICRON [Micron Technology]

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
22. V
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
24. Auto precharge mode only. The precharge timing budget (
25. Precharge mode only.
26. JEDEC and PC100, PC133 specify three clocks.
27.
28. Parameter guaranteed by design.
29. For -75, CL = 3,
30. CKE is HIGH during refresh command period
cannot be greater than one-third of the cycle rate. V
a pulse width ≤ 3ns for all inputs. V
a pulse width ≤ 3ns, and the pulse width cannot be greater than one-third of the cycle
rate.
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including
used to reduce the data rate.
the first clock delay, after the last WRITE is executed.
t
limit is actually a nominal value and does not result in a fail value.
AC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.
IH
overshoot: V
t
CK = 7.5ns; for -7E, CL = 2,
IH
(MAX) = V
48
DD
Q + 2V for a pulse width ≤ 3ns, and the pulse width
t
WR, and PRECHARGE commands). CKE may be
IH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
overshoot for pin A12 is limited to V
t
CK = 7.5ns.
t
RFC (MIN) else CKE is LOW. The I
512Mb: x4, x8, x16 SDRAM
IL
undershoot: V
t
RP) begins 7.5ns/7ns after
©2000 Micron Technology, Inc. All rights reserved.
IL
(MIN) = –2V for
DD
Q + 1V for
Notes
DD
6