MT48LC128M4A2_07 MICRON [Micron Technology], MT48LC128M4A2_07 Datasheet - Page 31

• Manufacturer Part Number: MT48LC128M4A2_07
• Description: 512Mb x4, x8, x16 SDRAM
• Manufacturer: MICRON [Micron Technology]

Figure 22:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
WRITE-to-PRECHARGE
Note:
the PRECHARGE command is that it requires that the command and address buses be
available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE
command. When truncating a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in Figure 23 on page 32, where data n is
the last desired data element of a longer burst.
t WR @ t CLK > 15ns
COMMAND
COMMAND
t WR = t CLK < 15ns
ADDRESS
ADDRESS
DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
DQM
DQM
CLK
DQ
DQ
BANK a,
BANK a,
WRITE
WRITE
COL n
COL n
D
D
T0
n
n
IN
IN
n + 1
n + 1
NOP
NOP
D
D
T1
IN
IN
t
WR
31
PRECHARGE
(a or all)
BANK
NOP
T2
t
WR
PRECHARGE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(a or all)
BANK
NOP
T3
Transitioning Data
t RP
NOP
NOP
T4
512Mb: x4, x8, x16 SDRAM
t RP
BANK a,
ACTIVE
NOP
ROW
T5
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Don’t Care
BANK a,
ACTIVE
ROW
NOP
T6
Operations