MT48LC128M4A2_07 MICRON [Micron Technology], MT48LC128M4A2_07 Datasheet - Page 25

• Manufacturer Part Number: MT48LC128M4A2_07
• Description: 512Mb x4, x8, x16 SDRAM
• Manufacturer: MICRON [Micron Technology]

Figure 13:
Figure 14:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
READ-to-WRITE
READ-to-WRITE with Extra Clock Cycle
Note:
Note:
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 13
shows the case where the clock frequency allows for bus contention to be avoided
without adding a NOP cycle, and Figure 14 shows the case where the additional NOP is
needed.
COMMAND
COMMAND
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated), and a full-
page burst may be truncated with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL - 1. This is shown in Figure 15 on page 26 for
ADDRESS
ADDRESS
A CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank. If a burst of 1 is used, then DQM is not required.
CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank.
DQM
DQM
CLK
CLK
DQ
DQ
BANK,
T0
COL n
BANK,
COL n
READ
T0
READ
T1
T1
NOP
NOP
Transitioning Data
25
T2
T2
NOP
NOP
Transitioning Data
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
D
NOP
OUT
t
t HZ
D
HZ
t
n
OUT
CK
n
Don’t Care
BANK,
T4
COL b
WRITE
T4
NOP
D
IN
b
t
512Mb: x4, x8, x16 SDRAM
DS
Don’t Care
T5
BANK,
COL b
WRITE
D
IN
b
t
©2000 Micron Technology, Inc. All rights reserved.
DS
Operations