MT48LC128M4A2_07 MICRON [Micron Technology], MT48LC128M4A2_07 Datasheet - Page 27

no-image

MT48LC128M4A2_07

Manufacturer Part Number
MT48LC128M4A2_07
Description
512Mb x4, x8, x16 SDRAM
Manufacturer
MICRON [Micron Technology]
Datasheet
Figure 16:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Terminating a READ Burst
Note:
COMMAND
COMMAND
ADDRESS
ADDRESS
DQM is LOW.
CLK
CLK
DQ
DQ
BANK,
COL n
T0
T0
BANK,
COL n
READ
READ
CL = 2
T1
T1
NOP
NOP
CL = 3
27
T2
T2
NOP
NOP
D
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
NOP
n + 1
D
D
OUT
OUT
n
TERMINATE
TERMINATE
BURST
BURST
T4
T4
x = 1 cycle
n + 2
D
n + 1
D
Transitioning Data
OUT
OUT
512Mb: x4, x8, x16 SDRAM
x = 2 cycles
T5
T5
NOP
NOP
n + 3
n + 2
D
D
OUT
OUT
©2000 Micron Technology, Inc. All rights reserved.
T6
T6
NOP
NOP
n + 3
D
OUT
Operations
Don’t Care
T7
NOP

Related parts for MT48LC128M4A2_07