ADV7191 Analog Devices, ADV7191 Datasheet - Page 24
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ADV7191
Manufacturer Part Number
ADV7191
Description
Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
Manufacturer
Analog Devices
Datasheet
1.ADV7191.pdf
(69 pages)
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ADV7190/ADV7191
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7190/ADV7191 can generate Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is
disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the
rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 37 (NTSC) and Figure 38 (PAL). Figure 39
illustrates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7190/ADV7191 accepts Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC
and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an
Even Field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7190/ADV7191 automatically blanks all
normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 40 (NTSC) and Figure 41 (PAL).
HSYNC
HSYNC
BLANK
VSYNC
BLANK
VSYNC
522
260
523
261
HSYNC
BLANK
524
PIXEL
FIELD
DATA
DISPLAY
262
DISPLAY
525
263
NTSC = 16
PAL = 12
1
264
ODD FIELD
EVEN FIELD
2
CLOCK/2
CLOCK/2
265
3
266
4
267
5
268
VERTICAL BLANK
VERTICAL BLANK
PAL = 132
NTSC = 122
6
269
EVEN FIELD
ODD FIELD
7
270
CLOCK/2
CLOCK/2
8
271
9
272
10
273
Cb
11
274
Y
Cr
Y
20
283
DISPLAY
21
284
22
285
DISPLAY