ADV7191 Analog Devices, ADV7191 Datasheet
ADV7191
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ADV7191 Summary of contents
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... Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs GENERAL DESCRIPTION The ADV7190/ADV7191 is part of the new generation of video encoders from Analog Devices. The device builds on the perfor- mance of previous video encoders and provides new features such as, Digital Noise Reduction, Gamma Correction, 4× Oversam- pling and 54 MHz operation, Average Brightness Detection, Chroma Delay, an additional Chroma Filter, etc ...
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... ADV7190/ADV7191 CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1 SPECIFICATIONS Static Performance Static Performance 3 Dynamic Specification Dynamic Specification 3 Timing Characteristics Timing Characteristics 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 9 PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . . 9 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 10 DETAILED DESCRIPTION OF FEATURES ...
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... REF . PLL ADV7190/ADV7191 MIN MAX Unit Test Conditions Bits LSB LSB Guaranteed Monotonic V V µ 0 2 µA = 400 µ SOURCE 3.2 mA SINK µ 300 Ω 1200 Ω ...
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... DAC I CCT NOTES All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization × Oversampling Mode, the power re- 1 quirement for the ADV7190/ADV7191 are typically 3 Temperature range 0°C to 70°C. MIN ...
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... unless otherwise noted.) MIN MAX Min Typ Max 0.2 (0.5) 0.5 (0.2) 78.5 (78) 78 (78) 62.3 (62) 61 (62.5) 0.5 0.8 0.6 0.5 0.1 0 ADV7190/ADV7191 = 1200 unless otherwise noted. All SET1,2 Unit Test Conditions % Degrees dB rms RMS dB p-p Peak Periodic dB rms RMS dB p-p Peak Periodic Degrees % ± % Referenced to 40 IRE ± Degrees ± % ± ...
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... ADV7190/ADV7191 5 V TIMING CHARACTERISTICS Parameter 2 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK Rise Time SDATA, SCLOCK Fall Time Setup Time (Stop Condition), t ...
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... MHz 2 Clock Cycles 67 Clock Cycles MHz ADV7190/ADV7191 = 1200 unless otherwise noted. All SET1 Test Conditions After This Period the First Clock Is Generated Relevant for Repeated Start Condition ...
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... ADV7190/ADV7191 SDA SCL CLOCK HSYNC, CONTROL VSYNC, I/PS BLANK PIXEL INPUT DATA HSYNC, VSYNC, CONTROL BLANK, O/PS CSO_HSO, VSO, CLAMP TTXREQ t 16 CLOCK TTX 4 CLOCK CYCLES CLOCK 4 CLOCK CYCLES ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7190/ADV7191 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precau- tions are recommended to avoid performance degradation or loss of functionality ...
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... A 1200 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the Video Signals from DACs A, B, and C. The input resets the on-chip timing generator and sets the ADV7190/ADV7191 into default mode. See Appendix 8 for Default Register settings. Dual function CSO or HSO Output Sync Signal at TTL Level. ...
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... P15 PLL CLKIN CLKOUT Six DACs are available on the ADV7190/ADV7191, each of which is capable of providing 4. current. In addition to the composite output signal there is the facility to output S-Video (Y/C Video), RGB Video and YUV Video. All YUV formats (Betacam, MII and (SMPTE/EBU N10) are supported. ...
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... Cb typically have a range of 128+/–112; however possible to input data from 1 to 254 on both Y, Cb, and Cr. The ADV7190/ADV7191 supports PAL ( and NTSC M, N (with and without Pedestal) and PAL60 stan- dards. Digital Noise Reduction can be applied to the Y signal. ...
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... Monotonic 1.5 Passband 3 dB Bandwidth 1 Ripple (dB) (MHz) 0 0.09 1.395 1 Monotonic 0.65 0 Monotonic 1.0 1 0.048 2.2 0 Monotonic 3.2 1 Monotonic 0.65 0 Monotonic 0.5 ADV7190/ADV7191 Oversampling) 2 Stopband Stopband 3 Cutoff (MHz) Attentuation 6.05 –75.2 6.41 –64.6 8.03 –87.3 8.02 –79.7 8.03 –86.6 5.09 –62.6 3.74 –88.2 Oversampling) 2 Stopband Stopband 3 Cutoff (MHz) Attentuation 2.46 –83.9 2.41 –71.1 1.89 –64.43 3.1 –65.9 5.3 –84.5 2.41 – ...
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... ADV7190/ADV7191 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 – ...
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... ADV7190/ADV7191 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz ...
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... ADV7190/ADV7191 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 – ...
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... CVBS the phase between the video and the colorburst is modified and OUTPUT PIN hence the hue is shifted. The ADV7190/ADV7191 provides a range of ± 22° in increments of 0.17578125°. (Hue Adjust Register.) CLAMP ...
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... Mode Register 2 (i.e., control via I and Mode Register 6.) SQUARE PIXEL MODE The ADV7190/ADV7191 can be used to operate in square pixel mode. For NTSC operation an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz is required. The internal timing logic adjusts ac- cordingly for square pixel mode operation. Square pixel mode is not available in 4× ...
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... It is possible to operate all six DACs at 27 MHz (2× Oversam- pling MHz (4× Oversampling). The ADV7190/ADV7191 is supplied with a 27 MHz clock synced with the incoming data. Two options are available: to run the device throughout at 27 MHz or to enable the PLL. In the latter case, even if the incoming data runs at 27 MHz, 4× ...
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... The ADV7190/ADV7191 internal timing is under the control of the logic level on the NTSC_PAL pin. When RESET is released Y, Cr, Cb values corresponding to a black screen are input to the ADV7190/ADV7191. Output timing signals are still suppressed at this stage. DACs are switched off and DACs are switched on. ...
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... Mode 0 (CCIR–656): Slave Option (Timing Register 0 TR0 = The ADV7190/ADV7191 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace ...
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... Register 0 TR0 = The ADV7190/ADV7191 generates H, V, and F signals required for the SAV and EAV Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the VSYNC pin. Mode 0 is illustrated in Figure 34 (NTSC) and Figure 35 (PAL) ...
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... Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7190/ADV7191 accepts Horizontal SYNC and Odd/ Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624 ...
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... VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 40 (NTSC) and Figure 41 (PAL). ...
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... HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 40 (NTSC) and Figure 41 (PAL). Figure 42 illustrates the HSYNC, BLANK and VSYNC for an even-to-odd fi ...
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... In this mode the ADV7190/ADV7191 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7190/ADV7191 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 44 (NTSC) and Figure 45 (PAL). ...
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... Figure 46 and Figure 47. The LSB sets either a read or write operation. Logic Level 1 corresponds to a read operation while Logic Level 0 corresponds to a write opera- tion set by setting the ALSB pin of the ADV7190/ADV7191 to Logic Level 0 or Logic Level ...
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... ADV7190/ADV7191 REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7190/ADV7191 with the exception of the Subaddress Regis- ters, which are write-only registers. The Subaddress Register determines which register the next read or write operation ac- cesses. All communications with the part through the bus start with an access to the Subaddress Register ...
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... MR0 BIT DESCRIPTION Output Video Standard Selection (MR00–MR01) These bits are used to set up the encoder mode. The ADV7190/ ADV7191 can be set up to output NTSC, PAL ( I), PAL M or PAL N standard video. Luminance Filter Select (MR02–MR04) These bits specify which luma filter selected. The filter selection is made independent of whether PAL or NTSC is selected ...
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... ENABLE Standard I This bit controls the video standard used by the ADV7190/ ADV7191. When this bit is set to 1 the video standard as pro- grammed in Output Video Standard Selection (MR00, MR01). When MR25 is set to 0, the ADV7190/ADV7191 is forced into the standard selected by the NTSC_PAL pin. When NTSC_PAL is low the standard is NTSC, when the NTSC_PAL pin is high, the standard is PAL ...
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... If MR41 is set to one and MR42 is set to one, the SCRESET/ RTC/TR pin is configured as a real-time control input and the ADV7190/ADV7191 can be used to lock to an external video source working in RTC mode. For more information see Real-Time Control, Subcarrier Reset and Timing Reset section. ...
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... RGB outputs. Clamp Delay Value (MR54–MR55) These bits control the delay or advance of the CLAMP signal in the front or back porch of the ADV7190/ADV7191 pos- sible to delay or advance the pulse by zero, one, two, or three clock cycles. Note: Pin multifunctional pin (VSO/CLAMP). CLAMP/ VSO Select Control (MR77) has to be set accordingly ...
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... Power-Up Sleep Mode Control (MR60) After RESET is applied this control is enabled (MR60 = 0) if both SCRESET/RTC/TR and NTSC_PAL pins are tied high. The ADV7190/ADV7191 will then power up in Sleep Mode to facilitate low power consumption while the I When this control is disabled (MR60 = 1, via the I Mode control passes to Sleep Mode Control, MR27 ...
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... Register, Gamma Curve Select Bit and the Macrovision Registers. Double Buffering is not available in Master Timing mode. 16-Bit Pixel Port (MR83) This bit controls if the ADV7190/ADV7191 accepts 8-bit or 16-bit input data. In 8-bit mode the data will be input on Pins P0–P7. Unused pixel inputs should be grounded. Reserved (MR84) A Logic 0 must be written to this bit ...
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... These bits adjust the position of the HSYNC output relative to the VSYNC output one clock cycle at 27 MHz. PCLK HSYNC to VSYNC Rising Edge Control (TR14–TR15) When the ADV7190/ADV7191 is in Timing Mode 1, these bits 2 C register. adjust the position of the HSYNC output relative to the VSYNC output rising edge one clock cycle at 27 MHz ...
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... ADV7190/ADV7191 TR17 TR16 HSYNC TO PIXEL DATA ADJUST TR17 TR16 TIMING MODE 1 (MASTER/PAL) HSYNC VSYNC SUBCARRIER FREQUENCY REGISTERS 3–0 (FSC31–FSC0) (Address (SR4–SR0) = 0CH–0FH) These 8-bit-wide registers are used to set up the Subcarrier Fre- quency ...
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... TXE10 TXE9 TXE8 i.e., the CRC check sequence, is internally calculated by the ADV7190/ADV7191. If this bit is disabled (0), the CRC values in the register are output to the CGMS data stream. CGMS Odd Field Control (C/W05) When this bit is set (1), CGMS is enabled for odd fields. Note this is only valid in NTSC mode. ...
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... ADV7190/ADV7191 CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10) (Address (SR4–SR0) = 1AH) CGMS_WSS Register 8-bit-wide register. Figure 70 shows the operations under control of this register. C/W1 BIT DESCRIPTION CGMS/WSS Data (C/W10–C/W15) These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data. CGMS Data (C/W16– ...
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... The ADV7190/ADV7191 provides a range of ± 22.5° increments of 0.17578125°. For normal operation (zero adjust- ment) this register is set to 80Hex. FFHex and 00Hex represent the upper and lower limit (respectively) of adjustment attainable. Hue Adjust [° ...
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... ADV7190/ADV7191 Sharpness CONTROL REGISTER (PR) (Address (SR5–SR0) = 22H) The sharpness response register is an 8-bit-wide register. The four MSBs are set to 0. The four LSBs are written to in order to select a desired filter response. Figure 76 shows the operation under control of this register. PR BIT DESCRIPTION Sharpness Response Value (PR3– ...
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... Consider the coring gain po- sitions fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data. DNR27 – DNR24 = 01 HEX ADV7190/ADV7191 DNR12 DNR11 DNR10 11 10 ...
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... ADV7190/ADV7191 DNR27 DNR DNR DNR DNR • • • • • • GAMMA CORRECTION REGISTERS 0–13 (GAMMA CORRECTION 0–13) (Address (SR5–SR0) = 26H–32H) The Gamma Correction Registers are fourteen 8-bit-wide regis- ters. They are used to program the gamma correction Curves A and B ...
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... A Logic 0 must be written to this bit. OCR06 OCR05 OCR03 OCR02 OCR04 OCR03 – OCR02 OCR06 – OCR04 ONE MUST BE ZERO MUST BE WRITTEN TO WRITTEN TO THESE BITS THESE BITS ADV7190/ADV7191 OCR01 OCR00 OCR00 ZERO MUST BE WRITTEN TO THIS BIT CLKOUT PIN CONTROL OCR01 0 ENSABLED 1 DISABLED ...
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... Best performance is obtained with 0.1 µF ceramic capacitor decoupling. Each group of V pins on the ADV7190/ADV7191 must have at least one 0.1 µF decoupling capacitor to GND. These capacitors should be placed as close as possible to the device. ...
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... AA 10nF 0.1 F DAC A 300 DAC B 300 DAC C CONNECT DAC OUTPUTS 300 TO OPTIONAL OUTPUT FILTER AND BUFFER CIRCUIT DAC D 300 DAC E 300 DAC 300 5k 100 SCL 100 SDA R SET2 1.2k R SET1 1.2k AGND 18, 24, 26, 33, 39, 42, 55, 64 ADV7190/ADV7191 ) AA 5k MPU BUS ...
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... Scan Line 284. The data for this operation is stored in Closed Captioning Extended Data Registers 0 and 1. All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7190/ ADV7191 All pixel inputs are ignored during Lines 21 and 284 if closed captioning is enabled. 10.5 50 IRE ...
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... Bits C/W05 and C/W06 control whether or not CGMS data is outputed on ODD and EVEN fields. CGMS data can only be transmitted when the ADV7190/ADV7191 is configured in NTSC mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit, see Figure 94 ...
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... The ADV7190/ADV7191 supports Wide Screen Signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7190/ADV7191 is configured in PAL mode. The WSS data is 14-bits long, the function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a Start Code, see Figure 91. The bits are output from the confi ...
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... DEL (6.9375 × 10 Thus 37 TTX bits correspond to 144 clocks (27 MHz), each bit has a width of almost four clock cycles. The ADV7190/ADV7191 uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal which can be output on the CVBS and Y outputs. ...
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... FREQUENCY – Hz × 6.75 APPENDIX 6 OPTIONAL OUTPUT FILTER filter is not required if the outputs of the ADV7190/ADV7191 are connected to most analog monitors, or TVs; however, if the output signals are applied to a system where sampling is used (e.g., Digital TVs), a filter is required to prevent aliasing. FILTER O/P FILTER I – ...
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... External buffering is needed on the ADV7190/ADV7191 DAC outputs. The configuration in Figure 99 is recommended. When calculating absolute output full-scale current and voltage use the following equations: × OUT OUT LOAD × K)/ OUT REF K = 4.2146 constant, V REF V AA ADV7190/ADV7191 V REF DAC A ...
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... ADV7190/ADV7191 The ADV7190/ADV7191 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. NTSC (F = 3.5795454 MHz) SC Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 ...
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... Brightness Control Register 00Hex 22Hex Sharpness Response Register 00Hex 23Hex DNR 0 44Hex 24Hex DNR 1 20Hex 25Hex DNR 2 00Hex 35Hex Output Clock Register 70Hex ADV7190/ADV7191 = 4.43361875 MHz) SC Data 12Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex CBHex 8AHex ...
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... ADV7190/ADV7191 PAL 3.57561149 MHz) SC Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 05Hex Mode Register 5 06Hex Mode Register 6 07Hex Mode Register 7 08Hex Mode Register 8 09Hex Mode Register 9 0AHex Timing Register 0 0BHex Timing Register 1 ...
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... Gamma 10 xxHex 31Hex Gamma 11 xxHex 32Hex Gamma 12 xxHex 33Hex Gamma 13 xxHex 34Hex Brightness Detect Register 72Hex 35Hex Output Clock Register ADV7190/ADV7191 (PAL_NTSC = 1, PAL Selected) Data 01Hex 07Hex 08Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex ...
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... ADV7190/ADV7191 130.8 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 1067.7mV 286mV (pk-pk) 650mV 232.2mV 0mV 100 IRE 7.5 IRE 0 IRE –40 IRE APPENDIX 9 NTSC WAVEFORMS (WITH PEDESTAL) 835mV (pk-pk) 1268.1mV PEAK COMPOSITE 1048.4mV REF WHITE 714.2mV 387.6mV BLACK LEVEL BLANK LEVEL 334 ...
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... IRE 0 IRE –40 IRE 100 IRE 0 IRE –40 IRE 1101.6mV 307mV (pk-pk) 650mV 198.4mV 0mV 100 IRE 0 IRE –40 IRE ADV7190/ADV7191 PEAK COMPOSITE 1289.8mV REF WHITE 1052.2mV 714.2mV BLANK/BLACK LEVEL 338mV SYNC LEVEL 52.1mV 1052.2mV REF WHITE 714.2mV 338mV BLANK/BLACK LEVEL 52 ...
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... ADV7190/ADV7191 1284.2mV 1047.1mV 350.7mV 50.8mV 1047mV 350.7mV 50.8mV 1092.5mV 300mV (pk-pk) 650mV 207.5mV 0mV 1050.2mV 351.8mV 51mV PAL WAVEFORMS PEAK COMPOSITE 696.4mV BLANK/BLACK LEVEL 696.4mV BLANK/BLACK LEVEL 885mV (pk-pk) 698.4mV BLANK/BLACK LEVEL REF WHITE SYNC LEVEL REF WHITE SYNC LEVEL PEAK CHROMA BLANK/BLACK LEVEL ...
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... SMPTE LEVEL 118mV 0mV –118mV –232mV –350mV UV WAVEFORMS BETACAM LEVEL 82mV 0mV 0mV BETACAM LEVEL 76mV 0mV 0mV SMPTE LEVEL 57mV 0mV 0mV ADV7190/ADV7191 505mV 423mV 0mV –82mV –423mV –505mV 467mV 391mV 0mV –76mV –391mV –467mV 350mV 293mV 0mV –57mV –293mV –350mV ...
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... ADV7190/ADV7191 0.6 0.4 0.2 0.0 0.2 0.0 10.0 NOISE REDUCTION: 0.00 dB APL = 39.1% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0. 6.72 s 0.5 0.0 0.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL SLOW CLAMP TO 0. 6.72 s OUTPUT WAVEFORMS L608 20.0 30.0 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS L575 10.0 20.0 30.0 40.0 MICROSECONDS PRECISION MODE OFF NO FILTERING SYNCHRONOUS 40.0 50.0 60.0 SOUND-IN-SYNC OFF ...
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... LINE PAL NO FILTERING SLOW CLAMP TO 0. 6.72 s 100.0 0.5 50.0 0.0 0.0 F1 –50.0 L76 0.0 10.0 20.0 APL = 44.6% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0. 6.72 s ADV7190/ADV7191 30.0 40.0 50.0 MICROSECONDS NO BRUCH SIGNAL PRECISION MODE OFF SOUND-IN-SYNC OFF SYNCHRONOUS SYNC = A FRAMES SELECTED: 1 30.0 40.0 50.0 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS SYNC = A FRAMES SELECTED ...
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... ADV7190/ADV7191 100.0 0.6 0.4 50.0 0.2 0.0 0.0 –0.2 10.0 NOISE REDUCTION: 15.05dB APL = 44.7% 525 LINE NTSC SLOW CLAMP TO 0. 6.72 s 0.4 50.0 0.2 0.0 –0.2 –50.0 –0.4 0.0 NOISE REDUCTION: 15.05dB APL NEEDS SYNC = SOURCE! 525 LINE NTSC SLOW CLAMP L238 20.0 30.0 40.0 MICROSECONDS PRECISION MODE OFF NO FILTERING SYNCHRONOUS F1 L76 10.0 20.0 30.0 40.0 MICROSECONDS PRECISION MODE OFF ...
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... BLUE (B) 700 700 600 600 500 500 400 400 300 300 200 200 100 100 0 0 100 100 200 200 300 300 ADV7190/ADV7191 mV Pr(C) 250 200 150 100 50 0 –50 –100 –150 –200 –250 mV RED (C) 700 600 500 400 300 200 100 ...
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... ADV7190/ADV7191 COLOR BAR (NTSC) FIELD = 1 LINE = 21 LUMINANCE LEVEL (IRE) 99.6 69.0 100 50 0 GRAY YELLOW CHROMINANCE LEVEL (IRE) 0.0 62.1 100 50 0 GRAY YELLOW CHROMINANCE PHASE (DEGREE) 167.3 400 200 0 GRAY YELLOW AVERAGE 32 32 COLOR BAR (PAL) LINE = 570 LUMINANCE LEVEL (mV) 695.7 464.8 1000 500 ...
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... AVERAGE 32 LUMINANCE NONLINEARITY (PAL) MOD 5 STEP LINE = 570 pk-pk = 0.4 LUMINANCE NONLINEARITY (PERCENT) 100.0 99.90 99.6 113 111 109 107 105 103 101 AVERAGE 32 ADV7190/ADV7191 MOD 5 STEP WFM MIN = 0.00, MAX = 0.32, pk-pk = 0.32 0.30 0.15 0.24 0. MIN = 0.00, MAX = 0.16, pk-pk = 0.16 0.09 0.13 0.16 0. ...
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... ADV7190/ADV7191 CHROMINANCE NONLINEARITY(NTSC) WFM FIELD = 2, LINE = 217 CHROMINANCE AMPLITUDE ERROR (PERCENT) 0.5 0 –10 20IRE 40IRE CHROMINANCE PHASE ERROR (DEGREE) –0.0 0 –5 20IRE 40IRE CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 714mV) 0.0 0.1 0.2 0.1 0.0 –0.1 –0.2 20IRE 40IRE AVERAGE 32 32 CHROMINANCE AM/PM (NTSC) WFM FIELD = 2, LINE = 217 ...
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... NOISE LEVEL = –63.1dB RMS AMPLITUDE (0dB = 700mV p-p) BANDWIDTH 100kHz TO FULL (TILT NULL) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 ADV7190/ADV7191 WFM NOISE LEVEL = –79.1dB RMS MHz WFM NOISE LEVEL = –62.3dB RMS MHz ...
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... ADV7190/ADV7191 APL = 39. SOUND IN SYNC OFF APL = 45.1% YI –Q SETUP 7.5% APPENDIX 10 VECTOR PLOTS 75% 100 R 100% 75 SYSTEM LINE L608 ANGLE (DEG) 0.0 GAIN 1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V AND – SYSTEM LINE L76F1 ANGLE (DEG) 0 ...
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... Dimensions shown in inches and (mm). 64-Lead LQFP (ST-64) 0.640 (16.25) 0.063 (1.60) 0.630 (16.00) SQ MAX 0.030 (0.75) 0.620 (15.75) 0.024 (0.60) 64 0.018 (0.45) 1 SEATING 12 PLANE TYP TOP VIEW (PINS DOWN) 0.004 (0.102) MAX LEAD 16 10 COPLANARITY 0.031 (0.80) 0.014 (0.35) 0.007 (0.17) BSC MAX 7 0 ADV7190/ADV7191 49 48 0.555 (14.10) 0.551 (14.00) SQ 0.547 (13.90 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) ...