ADV7191 Analog Devices, ADV7191 Datasheet - Page 20

• Manufacturer Part Number: ADV7191
• Description: Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
• Manufacturer: Analog Devices

ADV7190/ADV7191
RESET SEQUENCE
When RESET becomes active the ADV7190/ADV7191 reverts to
the default output configuration (see Appendix 8 for register
settings). The ADV7190/ADV7191 internal timing is under the
control of the logic level on the NTSC_PAL pin.
When RESET is released Y, Cr, Cb values corresponding to a
black screen are input to the ADV7190/ADV7191. Output
timing signals are still suppressed at this stage. DACs A, B, C
are switched off and DACs D, E, F are switched on.
When the user requires valid data, Pixel Data Valid Control is
enabled (MR26 = 1) to allow the valid pixel data to pass through
PIXEL_DATA_VALID
DIGITAL TIMING
RESET
DAC D,
DAC E
DAC A,
DAC B,
DAC C
DAC F
MR26
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RESET
DIGITAL TIMING SIGNALS SUPPRESSED
OFF
0
the encoder. Digital output timing signals become active and the
encoder timing is now under the control of the Timing Registers.
If at this stage, the user wishes to select a different video standard
to that on the NTSC_PAL pin, Standard I
enabled (MR25 = 1) and the video standard required is selected
by programming Mode Register 0 (Output Video Standard
Selection). Figure 31 illustrates the RESET sequence timing.
BLACK VALUE WITH SYNC
BLACK VALUE
1
VALID VIDEO
VALID VIDEO
VALID VIDEO
TIMING ACTIVE
2
C Control should be