MT48LC16M4A2 Micron Technology, MT48LC16M4A2 Datasheet - Page 44

• Manufacturer Part Number: MT48LC16M4A2
• Description: SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
DQML, DQMU
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
t
t
t
t
t
t
t
t
AC(3)
AC(2)
AH
AS
CH
CL
CK(3)
CK(2)
CKH
CKS
COMMAND
A0-A9, A11
BA0, BA1
DQM /
CLK
CKE
A10
DQ
2. READ command not allowed or
3. x16: A8, A9 and A11 = “Don’t Care”
1.5
2.5
2.5
1.5
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
t CKS
t CMS
1
6
–
1
t AS
t AS
t AS
-6
ACTIVE
T0
ROW
ROW
BANK
5.5
t CMH
t CKH
–
t AH
t AH
t AH
t RCD
t RAS
t RC
0.8
1.5
2.5
2.5
7.5
0.8
1.5
7
-7E
t CK
T1
5.4
5.4
NOP
SINGLE READ – WITH AUTO PRECHARGE
0.8
1.5
2.5
2.5
7.5
0.8
1.5
10
-75
t CL
5.4
6
T2
NOP 2
t
RAS would be violated.
t CH
10
1
2
3
3
8
1
2
-8E
6
6
T3
NOP 2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ENABLE AUTO PRECHARGE
t CMS
44
COLUMN m 3
BANK
T4
READ
t CMH
CAS Latency
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
t
t
t
t
t
t
t
t
CMH
CMS
HZ(3)
HZ(2)
LZ
OH
RAS
RC
RCD
RP
T5
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1.5
42 120,000
60
18
18
1
1
2
t AC
t RP
-6
5.5
–
D
T6
OUT
0.8
1.5
NOP
37 120,000
60
15
15
1
3
t OH
-7E
m
t HZ
1
64Mb: x4, x8, x16
5.4
5.4
ACTIVE
0.8
1.5
44 120,000
66
20
20
ROW
BANK
T7
ROW
1
3
-75
5.4
6
©2003, Micron Technology, Inc.
SDRAM
50 120,000
70
20
20
1
2
1
3
T8
-8E
NOP
DON’T CARE
UNDEFINED
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns