MT48LC16M4A2 Micron Technology, MT48LC16M4A2 Datasheet - Page 28

• Manufacturer Part Number: MT48LC16M4A2
• Description: SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page)
NOTE: 1. This table applies when CKE
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
CURRENT STATE CS# RAS#CAS# WE#
Row Active
Precharge
Precharge
Disabled)
Disabled)
(Auto
(Auto
Write
Read
Any
Idle
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
met (if the previous state was self refresh).
are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth
Table 4.
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Row Activating: Starts with registration of an ACTIVE command and ends when
Write w/Auto
Precharging: Starts with registration of a PRECHARGE command and ends when
Read w/Auto
Row Active: A row in the bank has been activated, and
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet termi-
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated
Idle: The bank has been precharged, and
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
n-1
no register accesses are in progress.
or been terminated.
nated or been terminated.
met, the bank will be in the idle state.
met, the bank will be in the row active state.
t
t
RP has been met. Once
RP has been met. Once
was HIGH and CKE
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
WRITE (Select column and start WRITE burst)
READ (Select column and start new READ burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
READ (Select column and start READ burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
PRECHARGE (Deactivate row in bank or banks)
WRITE (Select column and start WRITE burst)
BURST TERMINATE
WRITE (Select column and start new WRITE burst)
BURST TERMINATE
(Continued on next page)
n
is HIGH (see Truth Table 2) and after
28
t
t
RP is met, the bank will be in the idle state.
RP is met, the bank will be in the idle state.
t
RP has been met.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD has been met. No data bursts/accesses and
64Mb: x4, x8, x16
t
XSR has been
t
RCD is met. Once
t
RP is met. Once
©2003, Micron Technology, Inc.
SDRAM
t
RCD is
NOTES
t
RP is
11
10
10
10
10
10
10
7
7
8
8
9
8
9