TFA9881_1104 PHILIPS [NXP Semiconductors], TFA9881_1104 Datasheet - Page 5

• Manufacturer Part Number: TFA9881_1104
• Description: 3.4 W PDM input class-D audio amplifier
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
8. Functional description
TFA9881
Product data sheet
8.1 Mode selection and interfacing
8.2 Digital stereo PDM audio input
The TFA9881 is a high-efficiency mono Bridge Tied Load (BTL) class-D audio amplifier
with a digital stereo PDM input interface. A High-Pass (HP) filter removes the DC
components from the incoming PDM stream. This stream is subsequently converted into
two PWM signals. A 3-level PWM scheme supports filterless speaker drive.
The TFA9881 supports four operating modes:
The TFA9881 switches to Fault mode automatically when a protection mechanism is
activated (see
select the other three modes are given in
Power-down mode is selected when there is no clock signal on the CLK input. Applying
the clock signal will cause the TFA9881 to switch from Power-down mode to Operating
mode. Power-down mode is also activated when the power-down silence pattern (at least
128 consecutive 0xAC bytes) is detected on the DATA input (see
TFA9881 will switch to Power-down mode after byte 128 and will remain in Power-down
mode as long as a continuous stream of consecutive 0xAC bytes is being received. It will
switch to Operating mode if a byte other than 0xAC is received.
Mute mode is activated when the mute silence pattern (at least 32 consecutive 0x66
bytes) is detected on the DATA input. The TFA9881 will switch to Mute mode after byte 32
and will remain in Mute mode until a byte other than 0x66 is received.
Table 4.
The TFA9881 supports the digital stereo PDM stream illustrated in
shows the pin control configuration for left and right selection.
Mode
Power-down
Mute
Operating
•
•
•
•
Power-down mode, with low supply current
Mute mode, in which the output stages are floating so that the audio input signal is
suppressed
Operating mode, in which the amplifier is fully operational, delivering an output signal
Fault mode
Mode selection
Pins
CLK frequency
0 Hz
2 MHz to 8 MHz
2 MHz to 8 MHz
2 MHz to 8 MHz
Section
All information provided in this document is subject to legal disclaimers.
8.6). The defined patterns required on the CLK and DATA inputs to
Rev. 2 — 1 April 2011
Data pattern
don’t care
activated after 128 consecutive 0xAC bytes
activated after 32 consecutive 0x66 bytes
PDM bit stream
Table
3.4 W PDM input class-D audio amplifier
4.
Section
Figure
TFA9881
© NXP B.V. 2011. All rights reserved.
8.4.1). The
5.
OUTA, OUTB
floating
floating
floating
switching
Table 5
5 of 32