lc51024vg Lattice Semiconductor Corp., lc51024vg Datasheet - Page 8

• Manufacturer Part Number: lc51024vg
• Description: 3.3v In-system Programmable Superbig, Superwide High Density Plds Tm Tm
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 7. ispMACH 5000B Global Clock MUX
Power Management
The ispMACH 5000B devices provide unique power management controls. The device has two power settings,
high power and low power, on a per node basis. Low power consumption is approximately 50% of high power con-
sumption with a timing delay adder (t
as either high power or low power. However, care should be taken when sharing product terms between nodes with
different power settings.
The ispMACH 5000B devices also have a power-off feature for product terms that are not used. By default, any product
term that is not used is configured as such. This allows the device to operate at minimal power consumption without
affecting the timing of the design. For further information on power management, please refer to technical note number
TN1023, Power Estimation in ispMACH 5000B Devices available on the Lattice web site at www.latticesemi.com.
IEEE 1149.1-Compliant Boundary Scan Testability
All ispMACH 5000B devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows
functional testing of the circuit board on which the device is mounted through a serial scan path that can access all
critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly
onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be
linked into a board-level serial scan path for more board-level testing.
sysIO Quick Configuration
To facilitate the most efficient board test, the physical circuit configuration of the I/O cells must be set before run-
ning any continuity tests. As these tests are fast, by nature, the overhead and time that is required for configuration
of the I/Os should be minimal so that board test time is minimized. The ispMACH 5000B family of devices supports
this by offering the user the ability to quickly configure the I/O standard supported by the sysIO cells. This quick
configuration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed.
Lattice's ispVM™ System programming software can either perform the quick configuration through the PC parallel
port, or can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
In-system programming of devices provides a number of significant benefits including rapid prototyping, lower inven-
tory levels, higher quality, and the ability to make in-field modifications. All ispMACH 5000B devices provide in-system
programmability through their Boundary Scan Test Access Port. This capability has been implemented in a manner
GCLK0
GCLK1
GCLK2
GCLK3
VREF0
VREF1
VREF2
VREF3
LP
) to the routing delay of the low power node. Each node can be configured
+
–
+
–
–
+
–
+
8
ispMACH 5000B Family Data Sheet
CLK0
CLK1
CLK2
CLK3