lc51024vg Lattice Semiconductor Corp., lc51024vg Datasheet - Page 18

• Manufacturer Part Number: lc51024vg
• Description: 3.3v In-system Programmable Superbig, Superwide High Density Plds Tm Tm
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Timing Model
The task of determining the timing through the ispLSI 5000B family, just as any CPLD, is relatively simple. The tim-
ing model provided in Figure 8 shows the specific delay paths. Once the implementation of a given function is
determined either conceptually or from the design tool report file, the delay path of the function can easily be
derived from the timing model. The design tool reports the timing delays based on the same timing model for a par-
ticular design. Note that the internal timing parameters are given for reference only and are not tested. The external
timing parameters are tested and guaranteed for every device.
Figure 8. ispMACH 5000B Timing Model
CLK
RST
From Feedback
OE
IN
Note: Italicized parameters are delay adders above and beyond default conditions (i.e. GRP load of one GLB, CLK0, high-speed AND Array
and VCC I/O option).
t
Delays
GCLK_IN
In/Out
t
t
t
t
t
GOE
t
RST
t
IOI
IOI
IOI
IOI
IN
t
INREG
t
ROUTE
t
t
BLA
LP
t
t
t
PTCLK
t
PTSR
t
PTSA
BCLK
BSR
Control
Delays
t
PDb
t
GPTOE
t
PTOE
18
DATA
CE
S/R
Latch Delays
MC Reg
Register/
t
PDi
GLB Delays
ispMACH 5000B Family Data Sheet
Routing/
Q
Delays
In/Out
t
t
t
t
t
FBK
BUF
IOO
DIS
EN
OUT
Feedback