lc51024vg Lattice Semiconductor Corp., lc51024vg Datasheet - Page 37

• Manufacturer Part Number: lc51024vg
• Description: 3.3v In-system Programmable Superbig, Superwide High Density Plds Tm Tm
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Signal Descriptions
TMS
TCK
TDI
TDO
TOE
GOE0, GOE1
RESETB
yzz
GND
NC
V
GCLK0, GCLK1,
GCLK2, GCLK3
V
V
V
V
CC
REF0
REF2
CCO0
CCO2
Signal Names
, V
, V
, V
, V
REF1
REF3
CCO1
CCO3
,
,
Input - This pin is the Test Mode Select input, which is used to control the IEEE 1149.1 state machine.
Input - This pin is the Test Clock input pin, used to clock the IEEE 1149.1 state machine.
Input - This pin is the IEEE 1149.1 Test Data In pin, used to load data.
Output - This pin is the IEEE 1149.1 Test Data Out pin used to shift data out.
Input - Test Output Enable pin. TOE tristates all I/O pins when a logic low is driven.
Input - These two pins are the Global Output Enable input pins.
Dedicated Reset Input - This pin resets all registers in the devices. The global polarity (active high or low
input) for this pin is selectable.
Input/Output – These are the general purpose I/O used by the logic array. y is the GLB reference (alpha)
and z is the macrocell reference (numeric). z: 0-31
ispMACH 5128B
ispMACH 5256B
ispMACH 5384B
ispMACH 5512B
Ground
No connect
Vcc - These are the power supply pins for the logic core.
Inputs - These pins are dedicated CLK inputs.
Inputs - These are the reference supplies for the I/O banks.
V
CC
- These are the V
CC
y: A-D, z: 0-31
y: A-H, z: 0-31
y: A-L, z: 0-31
y: A-P, z: 0-31
supplies for each I/O bank.
37
Description
ispMACH 5000B Family Data Sheet