PSMN5R0-30YL_10 NXP [NXP Semiconductors], PSMN5R0-30YL_10 Datasheet - Page 8
![no-image](/images/no-image-200.jpg)
PSMN5R0-30YL_10
Manufacturer Part Number
PSMN5R0-30YL_10
Description
N-channel TrenchMOS logic level FET
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PSMN5R0-30YL_10.pdf
(14 pages)
NXP Semiconductors
PSMN5R0-30YL_3
Product data sheet
Fig 13. Normalized drain-source on-state resistance
Fig 15. Gate-source voltage as a function of gate
V
a
(V)
1.5
0.5
GS
10
2
1
0
8
6
4
2
0
−60
factor as a function of junction temperature
charge; typical values
0
V
10
0
DS
= 12 (V)
60
20
V
DS
= 19 (V)
120
30
All information provided in this document is subject to legal disclaimers.
Q
003aac551
T
G
j
( ° C)
(nC)
03aa27
180
40
Rev. 03 — 4 January 2010
Fig 14. Gate charge waveform definitions
Fig 16. Input, output and reverse transfer capacitances
2500
2000
1500
1000
(pF)
500
C
0
10
as a function of drain-source voltage; typical
values
V
V
V
V
-1
GS(pl)
DS
GS(th)
GS
C
C
C
N-channel TrenchMOS logic level FET
oss
rss
iss
Q
GS1
I
Q
1
PSMN5R0-30YL
D
GS
Q
GS2
Q
G(tot)
Q
GD
10
© NXP B.V. 2010. All rights reserved.
V
DS
003aaa508
003aac557
(V)
10
2
8 of 14