PLL602-35 PhaseLink (PLL), PLL602-35 Datasheet - Page 2

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PLL602-35

Manufacturer Part Number
PLL602-35
Description
, 12 - 24MHz In, 750kHz - 800MHz Out, Pecl, 3.3V
Manufacturer
PhaseLink (PLL)
Datasheet
FREQUENCY SELECTION TABLE
Note: SEL0 is not available (always “1”) for PLL602-35 and PLL602-38 in 3x3mm package
PIN DESCRIPTIONS PLL602-35 and PLL602-38 (see next page of PLL602-37/-39)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Name
XOUT
SEL3
CLKT
CLKC
SEL0
SEL1
SEL2
SEL3
GND
VDD
XIN
OE
1
0
0
0
1
1
1
1
1
1
Pin number
7,8,9,10,14
TSSOP
SEL2
1, 12
0
1
1
0
0
0
1
1
1
1
11
13
16
15
2
3
6
5
4
3x3mm QFN
Pin number
Not available
1,2,3,4,8,11
750kHz – 800MHz Low Phase Noise Multiplier XO
SEL1
6,10
1
1
1
0
1
1
0
0
1
1
12
13
16
15
14
5
7
9
Preliminary
Type
O
O
P
P
I
I
I
I
I
I
I
SEL0
1
0
1
1
0
1
0
1
0
1
Crystal in connector.
Crystal out connector.
Output enable pin (see OE logic state table on page 1).
GND.
True output PECL
Complementary output PECL.
Multiplier selector pins. These pins have an internal pull-up
that will default SEL to ‘1’ when not connected to GND.
+3.3V VDD.
PLL602-35/-37/-38/-39
Fin x 32
Fin / 8
Fin x 2
Fin / 2
Fin / 16
Fin x 4
Fin / 4
Fin x 8
Fin x 16
No multiplication
Selected Multiplier
Description
Universal Low Phase Noise IC’s
Rev 10/29/02 Page 2

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