PLL602-00 PhaseLink (PLL), PLL602-00 Datasheet

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PLL602-00

Manufacturer Part Number
PLL602-00
Description
, 12 - 25MHz In, 24 - 200MHz Out, CMOS, 3.3V
Manufacturer
PhaseLink (PLL)
Datasheet
FEATURES
DESCRIPTION
The PLL602-00 is a monolithic low jitter and low
phase noise (-135dBc @10kHz offset), high
performance CMOS XO IC Die, using a low cost
crystal (12-25MHz).
The same die can be used as a XO with output
frequencies ranging from F
to selector pads allowing bonding options (see
Divider Selection Table on this page). This makes
the PLL602-00 ideal for a wide range of applications
from 12MHz to 200MHz (including 50MHz,
77.76MHz, 125MHz and 155.52MHz, etc.).
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
XIN
DIE SPECIFICATIONS
Pad dimensions
Integrated crystal oscillator circuitry (XO).
Low phase noise (-135dBc @ 10kHz offset)
selectable frequency multipliers (x2, x4, x1, x8
as bonding options).
3.3V supply voltage.
Uses inexpensive fundamental-mode parallel
resonant crystals (from 12 to 25MHz).
12mA output drive capability at TTL level.
Selectable High Drive or Standard CMOS.
Available in DIE (65 mil x 62 mil).
Reverse side
Thickness
Name
Size
Multiplier XO IC Die for 12 to 25MHz Parallel Resonant Crystals
XO
80 micron x 80 micron
XIN
Selectable
x 1 to F
62 x 65 mil
PLL
Value
10 mil
GND
XIN
x 8 thanks
CLK
DIE CONFIGURATION
MULTIPLIER SELECTION
Note: - Selector pads default to ‘0’, wire bond to VDD to set to ‘1’
PAD DESCRIPTION
FS[0:2]
S2
Y
Name
0
0
0
1
0
1
1
1
GND
XTB
VDD
CLK
OE
SELECTION
XT
X
- (*) High-drive CMOS output
(0,0)
S1
0
0
1
0
1
1
0
1
27
29
OE
25
18,19,20
21,22,23
Number
XT
XTB
7,10
S0
27
29
13
25
0
1
0
0
1
0
1
1
Preliminary
VDD
23
12MHz – 25MHz
VDD
21
Crystal input connection.
Crystal connection.
Ground.
Clock Output.
Frequency selection pad
3.3V Power Supply.
Output Enable: ‘0’ to disable
(tri-state output), 1’ (default
value when not connected) to
enabled the output.
65 mil
FS0
20
F
PLL602-00
XIN
Description
FS1
19
GND
7
FS2
18
GND
CLK
Rev 1/07/03 Page 1
13
10
CLK (MHz)
(1550,1475)
F
F
F
F
F
F
F
F
XIN
XIN
XIN
XIN
XIN
XIN
XIN
XIN
x 4*
x 2*
x 1*
x 8*
x 2
x 4
x 1
x 8

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PLL602-00 Summary of contents

Page 1

... TTL level. Selectable High Drive or Standard CMOS. Available in DIE (65 mil x 62 mil). DESCRIPTION The PLL602- monolithic low jitter and low phase noise (-135dBc @10kHz offset), high performance CMOS XO IC Die, using a low cost crystal (12-25MHz). The same die can be used with output ...

Page 2

... -12mA 12mA -4mA OHC OH At TTL level (High drive) At TTL level (Low drive) Human Body Model, all pads except XT and XTB Human Body Model, XT and XTB pads PLL602-00 Preliminary MIN. MAX 0 ...

Page 3

... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 SYMBOL CONDITIONS 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load 2.0V ~ 0.8V with 10 pF load 3.0V ~ 0.3V with 15pF load Measured @ 1.4V Short Term SYMBOL CONDITIONS Parallel Fundamental Mode F XIN C (xtal cut R E PLL602-00 Preliminary MIN. TYP. MAX. UNITS 12 25 MHz 1.5 3.7 5 1.5 3 100 mA 50 MIN ...

Page 4

... VDD and GND. 44MHz @100Hz offset 44MHz @1kHz offset 44MHz @10kHz offset 44MHz @100kHz offset 44MHz @1MHz offset 155MHz @100Hz offset 155MHz @1kHz offset 155MHz @10kHz offset 155MHz @100kHz offset 155MHz @1MHz offset PLL602-00 Preliminary MIN. TYP. MAX. UNITS -80 ...

Page 5

... Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL602- PLL602-00 Preliminary TEMPERATURATRE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE D=DIE Rev 1/07/03 Page 5 ...

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