PLL602-35 PhaseLink (PLL), PLL602-35 Datasheet

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PLL602-35

Manufacturer Part Number
PLL602-35
Description
, 12 - 24MHz In, 750kHz - 800MHz Out, Pecl, 3.3V
Manufacturer
PhaseLink (PLL)
Datasheet
FEATURES
DESCRIPTIONS
The PLL602-35 (PECL with inverted OE), PLL602-37
(CMOS), PLL602-38 (PECL), and PLL602-39 (LVDS)
are high performance and low phase noise XO IC
chips. They provide phase noise performance as low
as –125dBc at 1kHz offset (at 155MHz), by multiply-
ing the input crystal frequency up to 32x. They ac-
cept fundamental parallel resonant mode crystals
from 12 to 25MHz.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
SEL
X+
X-
Selectable 750kHz to 800MHz range.
Low phase noise output (@ 10kHz frequency
offset, -140dBc/Hz for 19.44MHz, -127dBc/Hz for
106.25MHz, -125dBc/Hz for 155.52MHz, -
110dBc/Hz for 622.08MHz).
CMOS (PLL602-37), PECL (PLL602-35 and
PLL602-38) or LVDS (PLL602-39) output.
12 to 25MHz crystal input.
No external load capacitor or varicap required.
Output Enable selector.
Selectable 1/16 to 32x frequency multiplier.
3.3V operation.
Available in 16-Pin (TSSOP or 3x3mm QFN).
Oscillator
Amplifier
PLL by-pass
(Phase
Locked
Loop)
PLL
PLL602-3x
750kHz – 800MHz Low Phase Noise Multiplier XO
OE
Q
Q
Preliminary
^: Internal pull-up
*:
OUTPUT ENABLE LOGICAL LEVELS
OE input: Logical states defined by PECL levels for PLL602-38
PLL602-35/-37/-38/-39
PLL602-38
PLL602-35
PLL602-37
PLL602-39
On 3x3 package, PLL602-35/-38 do not have SEL0 available: Pin
10 is VDD, pin 11 is GND. However, PLL602-37/-39 have SEL0
(pin 10), and pin 11 is VDD. See pin assignment table for details.
Part #
Logical states defined by CMOS levels for PLL602-35/-37/-39
SEL3^
SEL2^
PIN CONFIGURATION
SEL3^
SEL2^
XOUT
XOUT
GND
GND
VDD
XIN
OE
OE
0 (Default)
1 (Default)
OE
(Top View)
1
0
14
15
13
16
1
2
3
4
5
6
7
8
Universal Low Phase Noise IC’s
12
PLL602-3x
1
11
2
Output enabled
Tri-state
Tri-state
Output enabled
10
3
9
16
15
14
13
12
11
10
4
9
State
Rev 10/29/02 Page 1
8
7
6
5
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
GND
CLKT
CLKC
VDD

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PLL602-35 Summary of contents

Page 1

... Low Phase Noise Multiplier XO ^: Internal pull- 3x3 package, PLL602-35/-38 do not have SEL0 available: Pin 10 is VDD, pin 11 is GND. However, PLL602-37/-39 have SEL0 (pin 10), and pin 11 is VDD. See pin assignment table for details. OUTPUT ENABLE LOGICAL LEVELS ...

Page 2

... Note: SEL0 is not available (always “1”) for PLL602-35 and PLL602-38 in 3x3mm package PIN DESCRIPTIONS PLL602-35 and PLL602-38 (see next page of PLL602-37/-39) TSSOP Name Pin number XIN 2 XOUT GND 7,8,9,10,14 CLKT 11 CLKC 13 SEL0 ...

Page 3

... PIN DESCRIPTIONS PLL602-37/-39 (see previous page of PLL602-35/-38) TSSOP Name Pin number XIN 2 XOUT GND 7,8,9,10,14 CLKT 11 CLKC 13 SEL0 16 SEL1 15 SEL2 5 SEL3 4 VDD 1, 12 ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature ...

Page 4

... Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Short Circuit Current 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL602-35/-37/-38/-39 Preliminary 750kHz – 800MHz Low Phase Noise Multiplier XO SYMBOL CONDITIONS Parallel Fundamental Mode ...

Page 5

... Phase noise specifications PARAMETERS FREQUENCY 19.44MHz 106.25MHz Phase Noise relative to carrier 155.52MHz 622.08MHz 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL602-35/-37/-38/-39 Preliminary 750kHz – 800MHz Low Phase Noise Multiplier XO CONDITIONS FREQUENCY 19.44MHz 77.76MHz 155.52MHz 622.08MHz 155.52MHz 155 ...

Page 6

... LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time LVDS Levels Test Circuit OUT OUT 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL602-35/-37/-38/-39 Preliminary 750kHz – 800MHz Low Phase Noise Multiplier XO SYMBOL CONDITIONS ...

Page 7

... Duty Cycle PECL Levels Test Circuit OUT 50 50 OUT OUT 80% 50% 20% OUT 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL602-35/-37/-38/-39 Preliminary 750kHz – 800MHz Low Phase Noise Multiplier XO CONDITIONS – 2V (see figure) ...

Page 8

... Symbol Min. Max. A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 9.80 10.00 E 3.80 4.00 H 5.80 6.20 L 0.40 1.27 e 1.27 BSC 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL602-35/-37/-38/-39 Preliminary 750kHz – 800MHz Low Phase Noise Multiplier XO TSSOP Min. Max. - 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 A1 0.65 BSC e Universal Low Phase Noise IC’ ...

Page 9

... LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex- press written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL602-35/-37/-38/-39 Preliminary 750kHz – 800MHz Low Phase Noise Multiplier XO 47745 Fremont Blvd ...

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