A2505PM-F AMICC [AMIC Technology], A2505PM-F Datasheet - Page 21

• Manufacturer Part Number: A2505PM-F
• Description: 16 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
• Manufacturer: AMICC [AMIC Technology]

Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh).
Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the
Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip
Select (
Data Input (DIO). Chip Select (
entire duration of the sequence.
The instruction sequence is shown in Figure 14. Chip Select
(
code has been latched in, otherwise the Bulk Erase
Figure 14. Bulk Erase (BE) Instruction Sequence
PRELIMINARY
S
) must be driven High after the eighth bit of the instruction
S
) Low, followed by the instruction code on Serial
(April, 2007, Version 0.6)
S
DIO
or
) must be driven Low for the
C
S
Notes: Address bits A23 to A21 are Don’t Care.
0
1 2 3
Instruction
20
instruction is not executed. As soon as Chip Select (
driven High, the self-timed Bulk Erase cycle (whose duration
is t
the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit
is 1 during the self-timed Bulk Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all
Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase
(BE) instruction is ignored if one, or more, sectors are
protected.
BE
4 5 6 7
) is initiated. While the Bulk Erase cycle is in progress,
AMIC Technology Corp.
A25L16P Series
S
) is