A2505PM-F AMICC [AMIC Technology], A2505PM-F Datasheet - Page 13

• Manufacturer Part Number: A2505PM-F
• Description: 16 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
• Manufacturer: AMICC [AMIC Technology]

Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new
values to be written to the Status Register. Before it can be
accepted,
previously have been executed. After the Write Enable
(WREN) instruction has been decoded and executed, the
device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by
driving Chip Select (
and the data byte on Serial Data Input (DIO).
The instruction sequence is shown in Figure 7. The Write
Status Register (WRSR) instruction has no effect on b6, b5,
b1 and b0 of the Status Register. b6 and b5 are always read
as 0.
Chip Select (
the data byte has been latched in. If not, the Write Status
Register (WRSR) instruction is not executed. As soon as
Chip Select (
Register cycle (whose duration is t
Figure 7. Write Status Register (WRSR) Instruction Sequence
PRELIMINARY
a
S
S
Write
) must be driven High after the eighth bit of
) is driven High, the self-timed Write Status
(April, 2007, Version 0.6)
S
) Low, followed by the instruction code
Enable
DIO
DO
S
C
(WREN)
W
) is initiated. While the
0 1
instruction
High Impedance
2 3 4
Instruction
must
5 6
12
Write Status Register cycle is in progress, the Status
Register may still be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0
when it is completed. When the cycle is completed, the Write
Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the
user to change the values of the Block Protect (BP2, BP1,
BP0) bits, to define the size of the area that is to be treated
as read-only, as defined in Table 1. The Write Status
Register (WRSR) instruction also allows the user to set or
reset the Status Register Write Disable (SRWD) bit in
accordance with the Write Protect (
Register Write Disable (SRWD) bit and Write Protect (
signal allow the device to be put in the Hardware Protected
Mode (HPM). The Write Status Register (WRSR) instruction
is not executed once the Hardware Protected Mode (HPM) is
entered.
7
MSB
7
8
6
9
Register In
10
Status
5
11 12 13 14 15
4
3
2
1
AMIC Technology Corp.
0
A25L16P Series
W
) signal. The Status
W
)