PLL202-14 PhaseLink (PLL), PLL202-14 Datasheet - Page 2

• Manufacturer Part Number: PLL202-14
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Power Mgt, Wdt, Drive Ctrl, SST
• Manufacturer: PhaseLink (PLL)

PIN DESCRIPTIONS
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
PCI_F, PCI(0:7)
24_48MHz/FS2*
CPU_STOP/
48MHz/FS3*
WDRESET#
REF1/FS4*
PCI_STOP
APIC(0:2)
CPU(0:2)
AGP(0:2)
FS1,FS0
SDATA
VDDL1
VDDL2
Name
VDD1
VDD2
VDD3
VDD4
XOUT
SCLK
REF0
GND
PD#
XIN
2,8,12,19,25,30,
9,10,11,13,14,
16,17,18,20
Number
36,40,43
39,38,35
23,26,27
45,44,42
Programmable Clock Generator for VIA Apollo Pro-266
47,6,7
15,24
37,41
21,22
31
46
32
33
34
29
28
48
1
5
3
4
Type
O
O
O
O
O
O
P
P
P
P
P
P
P
B
B
B
I
I
I
I
I
Power supply for REF(0:1), crystal oscillator and PLL core.
Power supply for 48MHz or 24_48MHz.
Power supply for PCI(0:7), PCI_F.
Power supply for AGP(0:2).
Power supply for APIC(0:2) (2.5V).
Power supply for CPU(0:2) (2.5V).
Ground.
14.318MHz crystal input to be connected to one end of the crystal.
14.318MHz crystal output.
PD is Asynchronous active low input used to power down the device into
a low power state. The internal clocks are disabled and the VCO and the
crystal are stopped.
When input is LOW, PCI_STOP will stop PCI(0:7) except PCI_F.
When input is LOW, CPU_STOP will stop CPU(0:2). The enable of the
watchdog timer masks the CPU_STOP action.
PCI clocks with frequencies defined by Frequency Table. These pins
except PCI_F will be LOW when PCI_STOP is LOW.
CPU clocks with frequencies defined by Frequency Table. These pins
are LOW when CPU_STOP is LOW.
AGP clocks outputs defined as 2x PCI.
Serial data input for serial interface port.
At power up, these pins are input pins and will determine the CPU clock
frequency. After input sampling, these pins will generate output clocks.
They all have internal pull up.
At power up, these pins will determine the CPU clock frequency.
2.5V APIC clock output running synchronous with PCI/2 clock output. It
is controlled by I2C byte 5 and byte 1.
3.3V 14.318MHz clock output.
Description
PLL202-14
Rev 3/23/01 Page 2