PLL202-11D PhaseLink (PLL), PLL202-11D Datasheet - Page 5
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PLL202-11D
Manufacturer Part Number
PLL202-11D
Description
Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Wdt, SST
Manufacturer
PhaseLink (PLL)
Datasheet
1.PLL202-11D.pdf
(14 pages)
2. BYTE 1: CPU Clock Register (1=Enable, 0=Disable)
3. BYTE 2: PCI Clock Register (1=Enable, 0=Disable)
4. BYTE 3: SDRAM Clock Register (1=Enable, 0=Disable)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Bit
Motherboard Clock Generator for 440BX Type with 133MHz FSB
21,20,18,17
32,31,29,28
38,37,35,34
Pin#
Pin#
Pin#
46
40
43
44
13
12
11
10
26
26
25
7
8
-
-
-
-
-
-
-
-
Default
Default
Default
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
Inverted Power on latched FS2 value (Read only)
Reserved
Reserved
Reserved
SDRAM_F ( Active/Inactive )
Reserved
CPU1 ( Active/Inactive )
CPU_F (Active/Inactive)
Description
Reserved
PCI_F ( Active/Inactive )
Reserved
PCI4 ( Active/Inactive )
PCI3 ( Active/Inactive )
PCI2 ( Active/Inactive )
PCI1 ( Active/Inactive )
PCI0 ( Active/Inactive )
Description
Reserved
Inverted Power on latched FS0 value (Read only)
48MHz
24MHz
Reserved
SDRAM ( 8:11 ) ( Active/Inactive )
SDRAM ( 4:7 ) ( Active/Inactive )
SDRAM ( 0:3 ) ( Active/Inactive )
PLL202-11 rev. D
Rev D 10/19/00 Page 5