DS28CN01U+ MAXIM [Maxim Integrated Products], DS28CN01U+ Datasheet - Page 7

• Manufacturer Part Number: DS28CN01U+
• Manufacturer: MAXIM [Maxim Integrated Products]

Acknowledged by Slave
A slave device, when addressed, is usually obliged to generate an acknowledge after the receipt of each byte. The
master must generate the clock pulse for each acknowledge bit. A slave that acknowledges must pull down the
SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock
pulse. Setup and hold times t
Acknowledged by Master
To continue reading from a slave, the master is obliged to generate an acknowledge after the receipt of each byte.
The master must generate the clock pulse for each acknowledge bit. A master that acknowledges must pull down
the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this
clock pulse. Setup and hold times t
Not Acknowledged by Slave
A slave device can be unable to receive or transmit data either because of an invalid access mode, because the
SHA-1 engine is running, or because an EEPROM write cycle is in progress. In this case, the DS28CN01 does not
acknowledge any bytes that it refuses by leaving SDA HIGH during the HIGH period of the acknowledge-related
clock pulse. See the Read and Write section for a detailed list of situations where the DS28CN01 does not
acknowledge.
Not Acknowledged by Master
At some time when receiving data, the master must terminate a read access. To achieve this, the master does not
acknowledge the last byte that it has received from the slave by leaving SDA high during the HIGH period of the
acknowledge-related clock pulse. In response, the slave stops transmitting, allowing the master to generate a
STOP condition.
Figure 3. I²C/SMBus Timing Diagram
Data Memory and Registers
For this section including Figures 4 to 5 and Tables 2 to 3 please refer to the full version of the data sheet.
Read and Write
This section discusses the read and write behavior of the EEPROM and the various registers. Please refer to the
full data sheet for details including Tables 4 to 13.
SHA-1 COMPUTATION ALGORITHM
This description of the SHA computation is adapted from the Secure Hash Standard SHA-1 document that can be
downloaded from the NIST website (http://www.itl.nist.gov/fipspubs/fip180-1.htm). Further details are found in the
full version of the data sheet.
NOTE: Timing is referenced to V
SCL
SDA
STOP START
t
BUF
t
HD:STA
t
LOW
SU:DAT
t
R
SU:DAT
and t
ILMAX
t
HD:DAT
HD:DAT
and t
and V
t
t
HD:DAT
F
HIGH
must be taken into account.
IHMIN
.
must be taken into account.
t
SU:DAT
7 of 9
Repeated
START
t
SU:STA
t
HD:STA
Suppression
Spike
t
SP
t
SU:STO